1373 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef GOYA_BLOCKS_H_14#define GOYA_BLOCKS_H_15 16#define mmPCI_NRTR_BASE 0x7FFC000000ull17#define PCI_NRTR_MAX_OFFSET 0x60818#define PCI_NRTR_SECTION 0x400019#define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull20#define PCI_RD_REGULATOR_MAX_OFFSET 0x7421#define PCI_RD_REGULATOR_SECTION 0x100022#define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull23#define PCI_WR_REGULATOR_MAX_OFFSET 0x7424#define PCI_WR_REGULATOR_SECTION 0x3B00025#define mmMME1_RTR_BASE 0x7FFC040000ull26#define MME1_RTR_MAX_OFFSET 0x60827#define MME1_RTR_SECTION 0x400028#define mmMME1_RD_REGULATOR_BASE 0x7FFC044000ull29#define MME1_RD_REGULATOR_MAX_OFFSET 0x7430#define MME1_RD_REGULATOR_SECTION 0x100031#define mmMME1_WR_REGULATOR_BASE 0x7FFC045000ull32#define MME1_WR_REGULATOR_MAX_OFFSET 0x7433#define MME1_WR_REGULATOR_SECTION 0x3B00034#define mmMME2_RTR_BASE 0x7FFC080000ull35#define MME2_RTR_MAX_OFFSET 0x60836#define MME2_RTR_SECTION 0x400037#define mmMME2_RD_REGULATOR_BASE 0x7FFC084000ull38#define MME2_RD_REGULATOR_MAX_OFFSET 0x7439#define MME2_RD_REGULATOR_SECTION 0x100040#define mmMME2_WR_REGULATOR_BASE 0x7FFC085000ull41#define MME2_WR_REGULATOR_MAX_OFFSET 0x7442#define MME2_WR_REGULATOR_SECTION 0x3B00043#define mmMME3_RTR_BASE 0x7FFC0C0000ull44#define MME3_RTR_MAX_OFFSET 0x60845#define MME3_RTR_SECTION 0x400046#define mmMME3_RD_REGULATOR_BASE 0x7FFC0C4000ull47#define MME3_RD_REGULATOR_MAX_OFFSET 0x7448#define MME3_RD_REGULATOR_SECTION 0x100049#define mmMME3_WR_REGULATOR_BASE 0x7FFC0C5000ull50#define MME3_WR_REGULATOR_MAX_OFFSET 0x7451#define MME3_WR_REGULATOR_SECTION 0xB00052#define mmMME_BASE 0x7FFC0D0000ull53#define MME_MAX_OFFSET 0xBB054#define MME_SECTION 0x800055#define mmMME_QM_BASE 0x7FFC0D8000ull56#define MME_QM_MAX_OFFSET 0x31057#define MME_QM_SECTION 0x100058#define mmMME_CMDQ_BASE 0x7FFC0D9000ull59#define MME_CMDQ_MAX_OFFSET 0x31060#define MME_CMDQ_SECTION 0x100061#define mmACC_MS_ECC_MEM_0_BASE 0x7FFC0DA000ull62#define ACC_MS_ECC_MEM_0_MAX_OFFSET 0x063#define ACC_MS_ECC_MEM_0_SECTION 0x100064#define mmACC_MS_ECC_MEM_1_BASE 0x7FFC0DB000ull65#define ACC_MS_ECC_MEM_1_MAX_OFFSET 0x066#define ACC_MS_ECC_MEM_1_SECTION 0x100067#define mmACC_MS_ECC_MEM_2_BASE 0x7FFC0DC000ull68#define ACC_MS_ECC_MEM_2_MAX_OFFSET 0x069#define ACC_MS_ECC_MEM_2_SECTION 0x100070#define mmACC_MS_ECC_MEM_3_BASE 0x7FFC0DD000ull71#define ACC_MS_ECC_MEM_3_MAX_OFFSET 0x072#define ACC_MS_ECC_MEM_3_SECTION 0x100073#define mmSBA_ECC_MEM_BASE 0x7FFC0DE000ull74#define SBA_ECC_MEM_MAX_OFFSET 0x075#define SBA_ECC_MEM_SECTION 0x100076#define mmSBB_ECC_MEM_BASE 0x7FFC0DF000ull77#define SBB_ECC_MEM_MAX_OFFSET 0x078#define SBB_ECC_MEM_SECTION 0x2100079#define mmMME4_RTR_BASE 0x7FFC100000ull80#define MME4_RTR_MAX_OFFSET 0x60881#define MME4_RTR_SECTION 0x400082#define mmMME4_RD_REGULATOR_BASE 0x7FFC104000ull83#define MME4_RD_REGULATOR_MAX_OFFSET 0x7484#define MME4_RD_REGULATOR_SECTION 0x100085#define mmMME4_WR_REGULATOR_BASE 0x7FFC105000ull86#define MME4_WR_REGULATOR_MAX_OFFSET 0x7487#define MME4_WR_REGULATOR_SECTION 0xB00088#define mmSYNC_MNGR_BASE 0x7FFC110000ull89#define SYNC_MNGR_MAX_OFFSET 0x440090#define SYNC_MNGR_SECTION 0x3000091#define mmMME5_RTR_BASE 0x7FFC140000ull92#define MME5_RTR_MAX_OFFSET 0x60893#define MME5_RTR_SECTION 0x400094#define mmMME5_RD_REGULATOR_BASE 0x7FFC144000ull95#define MME5_RD_REGULATOR_MAX_OFFSET 0x7496#define MME5_RD_REGULATOR_SECTION 0x100097#define mmMME5_WR_REGULATOR_BASE 0x7FFC145000ull98#define MME5_WR_REGULATOR_MAX_OFFSET 0x7499#define MME5_WR_REGULATOR_SECTION 0x3B000100#define mmMME6_RTR_BASE 0x7FFC180000ull101#define MME6_RTR_MAX_OFFSET 0x608102#define MME6_RTR_SECTION 0x4000103#define mmMME6_RD_REGULATOR_BASE 0x7FFC184000ull104#define MME6_RD_REGULATOR_MAX_OFFSET 0x74105#define MME6_RD_REGULATOR_SECTION 0x1000106#define mmMME6_WR_REGULATOR_BASE 0x7FFC185000ull107#define MME6_WR_REGULATOR_MAX_OFFSET 0x74108#define MME6_WR_REGULATOR_SECTION 0x3B000109#define mmDMA_NRTR_BASE 0x7FFC1C0000ull110#define DMA_NRTR_MAX_OFFSET 0x608111#define DMA_NRTR_SECTION 0x4000112#define mmDMA_RD_REGULATOR_BASE 0x7FFC1C4000ull113#define DMA_RD_REGULATOR_MAX_OFFSET 0x74114#define DMA_RD_REGULATOR_SECTION 0x1000115#define mmDMA_WR_REGULATOR_BASE 0x7FFC1C5000ull116#define DMA_WR_REGULATOR_MAX_OFFSET 0x74117#define DMA_WR_REGULATOR_SECTION 0x3B000118#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull119#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4120#define SRAM_Y0_X0_BANK_SECTION 0x1000121#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull122#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x334123#define SRAM_Y0_X0_RTR_SECTION 0x3000124#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC204000ull125#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4126#define SRAM_Y0_X1_BANK_SECTION 0x1000127#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC205000ull128#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x334129#define SRAM_Y0_X1_RTR_SECTION 0x3000130#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC208000ull131#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4132#define SRAM_Y0_X2_BANK_SECTION 0x1000133#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC209000ull134#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x334135#define SRAM_Y0_X2_RTR_SECTION 0x3000136#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC20C000ull137#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4138#define SRAM_Y0_X3_BANK_SECTION 0x1000139#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC20D000ull140#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x334141#define SRAM_Y0_X3_RTR_SECTION 0x3000142#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC210000ull143#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4144#define SRAM_Y0_X4_BANK_SECTION 0x1000145#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC211000ull146#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x334147#define SRAM_Y0_X4_RTR_SECTION 0xF000148#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC220000ull149#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4150#define SRAM_Y1_X0_BANK_SECTION 0x1000151#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC221000ull152#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x334153#define SRAM_Y1_X0_RTR_SECTION 0x3000154#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC224000ull155#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4156#define SRAM_Y1_X1_BANK_SECTION 0x1000157#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC225000ull158#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x334159#define SRAM_Y1_X1_RTR_SECTION 0x3000160#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC228000ull161#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4162#define SRAM_Y1_X2_BANK_SECTION 0x1000163#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC229000ull164#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x334165#define SRAM_Y1_X2_RTR_SECTION 0x3000166#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC22C000ull167#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4168#define SRAM_Y1_X3_BANK_SECTION 0x1000169#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC22D000ull170#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x334171#define SRAM_Y1_X3_RTR_SECTION 0x3000172#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC230000ull173#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4174#define SRAM_Y1_X4_BANK_SECTION 0x1000175#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC231000ull176#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x334177#define SRAM_Y1_X4_RTR_SECTION 0xF000178#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC240000ull179#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4180#define SRAM_Y2_X0_BANK_SECTION 0x1000181#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC241000ull182#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x334183#define SRAM_Y2_X0_RTR_SECTION 0x3000184#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC244000ull185#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4186#define SRAM_Y2_X1_BANK_SECTION 0x1000187#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC245000ull188#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x334189#define SRAM_Y2_X1_RTR_SECTION 0x3000190#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC248000ull191#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4192#define SRAM_Y2_X2_BANK_SECTION 0x1000193#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC249000ull194#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x334195#define SRAM_Y2_X2_RTR_SECTION 0x3000196#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC24C000ull197#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4198#define SRAM_Y2_X3_BANK_SECTION 0x1000199#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC24D000ull200#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x334201#define SRAM_Y2_X3_RTR_SECTION 0x3000202#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC250000ull203#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4204#define SRAM_Y2_X4_BANK_SECTION 0x1000205#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC251000ull206#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x334207#define SRAM_Y2_X4_RTR_SECTION 0xF000208#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC260000ull209#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4210#define SRAM_Y3_X0_BANK_SECTION 0x1000211#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC261000ull212#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x334213#define SRAM_Y3_X0_RTR_SECTION 0x3000214#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC264000ull215#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4216#define SRAM_Y3_X1_BANK_SECTION 0x1000217#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC265000ull218#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x334219#define SRAM_Y3_X1_RTR_SECTION 0x3000220#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC268000ull221#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4222#define SRAM_Y3_X2_BANK_SECTION 0x1000223#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC269000ull224#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x334225#define SRAM_Y3_X2_RTR_SECTION 0x3000226#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC26C000ull227#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4228#define SRAM_Y3_X3_BANK_SECTION 0x1000229#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC26D000ull230#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x334231#define SRAM_Y3_X3_RTR_SECTION 0x3000232#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC270000ull233#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4234#define SRAM_Y3_X4_BANK_SECTION 0x1000235#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC271000ull236#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x334237#define SRAM_Y3_X4_RTR_SECTION 0xF000238#define mmSRAM_Y4_X0_BANK_BASE 0x7FFC280000ull239#define SRAM_Y4_X0_BANK_MAX_OFFSET 0x4240#define SRAM_Y4_X0_BANK_SECTION 0x1000241#define mmSRAM_Y4_X0_RTR_BASE 0x7FFC281000ull242#define SRAM_Y4_X0_RTR_MAX_OFFSET 0x334243#define SRAM_Y4_X0_RTR_SECTION 0x3000244#define mmSRAM_Y4_X1_BANK_BASE 0x7FFC284000ull245#define SRAM_Y4_X1_BANK_MAX_OFFSET 0x4246#define SRAM_Y4_X1_BANK_SECTION 0x1000247#define mmSRAM_Y4_X1_RTR_BASE 0x7FFC285000ull248#define SRAM_Y4_X1_RTR_MAX_OFFSET 0x334249#define SRAM_Y4_X1_RTR_SECTION 0x3000250#define mmSRAM_Y4_X2_BANK_BASE 0x7FFC288000ull251#define SRAM_Y4_X2_BANK_MAX_OFFSET 0x4252#define SRAM_Y4_X2_BANK_SECTION 0x1000253#define mmSRAM_Y4_X2_RTR_BASE 0x7FFC289000ull254#define SRAM_Y4_X2_RTR_MAX_OFFSET 0x334255#define SRAM_Y4_X2_RTR_SECTION 0x3000256#define mmSRAM_Y4_X3_BANK_BASE 0x7FFC28C000ull257#define SRAM_Y4_X3_BANK_MAX_OFFSET 0x4258#define SRAM_Y4_X3_BANK_SECTION 0x1000259#define mmSRAM_Y4_X3_RTR_BASE 0x7FFC28D000ull260#define SRAM_Y4_X3_RTR_MAX_OFFSET 0x334261#define SRAM_Y4_X3_RTR_SECTION 0x3000262#define mmSRAM_Y4_X4_BANK_BASE 0x7FFC290000ull263#define SRAM_Y4_X4_BANK_MAX_OFFSET 0x4264#define SRAM_Y4_X4_BANK_SECTION 0x1000265#define mmSRAM_Y4_X4_RTR_BASE 0x7FFC291000ull266#define SRAM_Y4_X4_RTR_MAX_OFFSET 0x334267#define SRAM_Y4_X4_RTR_SECTION 0xF000268#define mmSRAM_Y5_X0_BANK_BASE 0x7FFC2A0000ull269#define SRAM_Y5_X0_BANK_MAX_OFFSET 0x4270#define SRAM_Y5_X0_BANK_SECTION 0x1000271#define mmSRAM_Y5_X0_RTR_BASE 0x7FFC2A1000ull272#define SRAM_Y5_X0_RTR_MAX_OFFSET 0x334273#define SRAM_Y5_X0_RTR_SECTION 0x3000274#define mmSRAM_Y5_X1_BANK_BASE 0x7FFC2A4000ull275#define SRAM_Y5_X1_BANK_MAX_OFFSET 0x4276#define SRAM_Y5_X1_BANK_SECTION 0x1000277#define mmSRAM_Y5_X1_RTR_BASE 0x7FFC2A5000ull278#define SRAM_Y5_X1_RTR_MAX_OFFSET 0x334279#define SRAM_Y5_X1_RTR_SECTION 0x3000280#define mmSRAM_Y5_X2_BANK_BASE 0x7FFC2A8000ull281#define SRAM_Y5_X2_BANK_MAX_OFFSET 0x4282#define SRAM_Y5_X2_BANK_SECTION 0x1000283#define mmSRAM_Y5_X2_RTR_BASE 0x7FFC2A9000ull284#define SRAM_Y5_X2_RTR_MAX_OFFSET 0x334285#define SRAM_Y5_X2_RTR_SECTION 0x3000286#define mmSRAM_Y5_X3_BANK_BASE 0x7FFC2AC000ull287#define SRAM_Y5_X3_BANK_MAX_OFFSET 0x4288#define SRAM_Y5_X3_BANK_SECTION 0x1000289#define mmSRAM_Y5_X3_RTR_BASE 0x7FFC2AD000ull290#define SRAM_Y5_X3_RTR_MAX_OFFSET 0x334291#define SRAM_Y5_X3_RTR_SECTION 0x3000292#define mmSRAM_Y5_X4_BANK_BASE 0x7FFC2B0000ull293#define SRAM_Y5_X4_BANK_MAX_OFFSET 0x4294#define SRAM_Y5_X4_BANK_SECTION 0x1000295#define mmSRAM_Y5_X4_RTR_BASE 0x7FFC2B1000ull296#define SRAM_Y5_X4_RTR_MAX_OFFSET 0x334297#define SRAM_Y5_X4_RTR_SECTION 0x14F000298#define mmDMA_QM_0_BASE 0x7FFC400000ull299#define DMA_QM_0_MAX_OFFSET 0x310300#define DMA_QM_0_SECTION 0x1000301#define mmDMA_CH_0_BASE 0x7FFC401000ull302#define DMA_CH_0_MAX_OFFSET 0x200303#define DMA_CH_0_SECTION 0x7000304#define mmDMA_QM_1_BASE 0x7FFC408000ull305#define DMA_QM_1_MAX_OFFSET 0x310306#define DMA_QM_1_SECTION 0x1000307#define mmDMA_CH_1_BASE 0x7FFC409000ull308#define DMA_CH_1_MAX_OFFSET 0x200309#define DMA_CH_1_SECTION 0x7000310#define mmDMA_QM_2_BASE 0x7FFC410000ull311#define DMA_QM_2_MAX_OFFSET 0x310312#define DMA_QM_2_SECTION 0x1000313#define mmDMA_CH_2_BASE 0x7FFC411000ull314#define DMA_CH_2_MAX_OFFSET 0x200315#define DMA_CH_2_SECTION 0x7000316#define mmDMA_QM_3_BASE 0x7FFC418000ull317#define DMA_QM_3_MAX_OFFSET 0x310318#define DMA_QM_3_SECTION 0x1000319#define mmDMA_CH_3_BASE 0x7FFC419000ull320#define DMA_CH_3_MAX_OFFSET 0x200321#define DMA_CH_3_SECTION 0x7000322#define mmDMA_QM_4_BASE 0x7FFC420000ull323#define DMA_QM_4_MAX_OFFSET 0x310324#define DMA_QM_4_SECTION 0x1000325#define mmDMA_CH_4_BASE 0x7FFC421000ull326#define DMA_CH_4_MAX_OFFSET 0x200327#define DMA_CH_4_SECTION 0x20000328#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull329#define CPU_CA53_CFG_MAX_OFFSET 0x218330#define CPU_CA53_CFG_SECTION 0x1000331#define mmCPU_IF_BASE 0x7FFC442000ull332#define CPU_IF_MAX_OFFSET 0x134333#define CPU_IF_SECTION 0x2000334#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull335#define CPU_TIMESTAMP_MAX_OFFSET 0x1000336#define CPU_TIMESTAMP_SECTION 0x3C000337#define mmMMU_BASE 0x7FFC480000ull338#define MMU_MAX_OFFSET 0x44339#define MMU_SECTION 0x10000340#define mmSTLB_BASE 0x7FFC490000ull341#define STLB_MAX_OFFSET 0x50342#define STLB_SECTION 0x10000343#define mmNORTH_THERMAL_SENSOR_BASE 0x7FFC4A0000ull344#define NORTH_THERMAL_SENSOR_MAX_OFFSET 0xE64345#define NORTH_THERMAL_SENSOR_SECTION 0x1000346#define mmMC_PLL_BASE 0x7FFC4A1000ull347#define MC_PLL_MAX_OFFSET 0x444348#define MC_PLL_SECTION 0x1000349#define mmCPU_PLL_BASE 0x7FFC4A2000ull350#define CPU_PLL_MAX_OFFSET 0x444351#define CPU_PLL_SECTION 0x1000352#define mmIC_PLL_BASE 0x7FFC4A3000ull353#define IC_PLL_MAX_OFFSET 0x444354#define IC_PLL_SECTION 0x1000355#define mmDMA_PROCESS_MON_BASE 0x7FFC4A4000ull356#define DMA_PROCESS_MON_MAX_OFFSET 0x4357#define DMA_PROCESS_MON_SECTION 0xC000358#define mmDMA_MACRO_BASE 0x7FFC4B0000ull359#define DMA_MACRO_MAX_OFFSET 0x15C360#define DMA_MACRO_SECTION 0x150000361#define mmDDR_PHY_CH0_BASE 0x7FFC600000ull362#define DDR_PHY_CH0_MAX_OFFSET 0x0363#define DDR_PHY_CH0_SECTION 0x40000364#define mmDDR_MC_CH0_BASE 0x7FFC640000ull365#define DDR_MC_CH0_MAX_OFFSET 0xF34366#define DDR_MC_CH0_SECTION 0x8000367#define mmDDR_MISC_CH0_BASE 0x7FFC648000ull368#define DDR_MISC_CH0_MAX_OFFSET 0x204369#define DDR_MISC_CH0_SECTION 0xB8000370#define mmDDR_PHY_CH1_BASE 0x7FFC700000ull371#define DDR_PHY_CH1_MAX_OFFSET 0x0372#define DDR_PHY_CH1_SECTION 0x40000373#define mmDDR_MC_CH1_BASE 0x7FFC740000ull374#define DDR_MC_CH1_MAX_OFFSET 0xF34375#define DDR_MC_CH1_SECTION 0x8000376#define mmDDR_MISC_CH1_BASE 0x7FFC748000ull377#define DDR_MISC_CH1_MAX_OFFSET 0x204378#define DDR_MISC_CH1_SECTION 0xB8000379#define mmGIC_BASE 0x7FFC800000ull380#define GIC_MAX_OFFSET 0x10000381#define GIC_SECTION 0x401000382#define mmPCIE_WRAP_BASE 0x7FFCC01000ull383#define PCIE_WRAP_MAX_OFFSET 0xDF4384#define PCIE_WRAP_SECTION 0x1000385#define mmPCIE_DBI_BASE 0x7FFCC02000ull386#define PCIE_DBI_MAX_OFFSET 0xC04387#define PCIE_DBI_SECTION 0x2000388#define mmPCIE_CORE_BASE 0x7FFCC04000ull389#define PCIE_CORE_MAX_OFFSET 0x9B8390#define PCIE_CORE_SECTION 0x1000391#define mmPCIE_DB_CFG_BASE 0x7FFCC05000ull392#define PCIE_DB_CFG_MAX_OFFSET 0xE34393#define PCIE_DB_CFG_SECTION 0x1000394#define mmPCIE_DB_CMD_BASE 0x7FFCC06000ull395#define PCIE_DB_CMD_MAX_OFFSET 0x810396#define PCIE_DB_CMD_SECTION 0x1000397#define mmPCIE_AUX_BASE 0x7FFCC07000ull398#define PCIE_AUX_MAX_OFFSET 0x9BC399#define PCIE_AUX_SECTION 0x1000400#define mmPCIE_DB_RSV_BASE 0x7FFCC08000ull401#define PCIE_DB_RSV_MAX_OFFSET 0x800402#define PCIE_DB_RSV_SECTION 0x8000403#define mmPCIE_PHY_BASE 0x7FFCC10000ull404#define PCIE_PHY_MAX_OFFSET 0x924405#define PCIE_PHY_SECTION 0x30000406#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull407#define PSOC_I2C_M0_MAX_OFFSET 0x100408#define PSOC_I2C_M0_SECTION 0x1000409#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull410#define PSOC_I2C_M1_MAX_OFFSET 0x100411#define PSOC_I2C_M1_SECTION 0x1000412#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull413#define PSOC_I2C_S_MAX_OFFSET 0x100414#define PSOC_I2C_S_SECTION 0x1000415#define mmPSOC_SPI_BASE 0x7FFCC43000ull416#define PSOC_SPI_MAX_OFFSET 0x100417#define PSOC_SPI_SECTION 0x1000418#define mmPSOC_EMMC_BASE 0x7FFCC44000ull419#define PSOC_EMMC_MAX_OFFSET 0xF70420#define PSOC_EMMC_SECTION 0x1000421#define mmPSOC_UART_0_BASE 0x7FFCC45000ull422#define PSOC_UART_0_MAX_OFFSET 0x1000423#define PSOC_UART_0_SECTION 0x1000424#define mmPSOC_UART_1_BASE 0x7FFCC46000ull425#define PSOC_UART_1_MAX_OFFSET 0x1000426#define PSOC_UART_1_SECTION 0x1000427#define mmPSOC_TIMER_BASE 0x7FFCC47000ull428#define PSOC_TIMER_MAX_OFFSET 0x1000429#define PSOC_TIMER_SECTION 0x1000430#define mmPSOC_WDOG_BASE 0x7FFCC48000ull431#define PSOC_WDOG_MAX_OFFSET 0x1000432#define PSOC_WDOG_SECTION 0x1000433#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull434#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000435#define PSOC_TIMESTAMP_SECTION 0x1000436#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull437#define PSOC_EFUSE_MAX_OFFSET 0x10C438#define PSOC_EFUSE_SECTION 0x1000439#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull440#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xA48441#define PSOC_GLOBAL_CONF_SECTION 0x1000442#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull443#define PSOC_GPIO0_MAX_OFFSET 0x1000444#define PSOC_GPIO0_SECTION 0x1000445#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull446#define PSOC_GPIO1_MAX_OFFSET 0x1000447#define PSOC_GPIO1_SECTION 0x1000448#define mmPSOC_BTL_BASE 0x7FFCC4E000ull449#define PSOC_BTL_MAX_OFFSET 0x124450#define PSOC_BTL_SECTION 0x1000451#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull452#define PSOC_CS_TRACE_MAX_OFFSET 0x0453#define PSOC_CS_TRACE_SECTION 0x1000454#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull455#define PSOC_GPIO2_MAX_OFFSET 0x1000456#define PSOC_GPIO2_SECTION 0x1000457#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull458#define PSOC_GPIO3_MAX_OFFSET 0x1000459#define PSOC_GPIO3_SECTION 0x1000460#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull461#define PSOC_GPIO4_MAX_OFFSET 0x1000462#define PSOC_GPIO4_SECTION 0x1000463#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull464#define PSOC_DFT_EFUSE_MAX_OFFSET 0x10C465#define PSOC_DFT_EFUSE_SECTION 0x1000466#define mmPSOC_PM_BASE 0x7FFCC54000ull467#define PSOC_PM_MAX_OFFSET 0x4468#define PSOC_PM_SECTION 0x1000469#define mmPSOC_TS_BASE 0x7FFCC55000ull470#define PSOC_TS_MAX_OFFSET 0xE64471#define PSOC_TS_SECTION 0xB000472#define mmPSOC_MII_BASE 0x7FFCC60000ull473#define PSOC_MII_MAX_OFFSET 0x105C474#define PSOC_MII_SECTION 0x10000475#define mmPSOC_EMMC_PLL_BASE 0x7FFCC70000ull476#define PSOC_EMMC_PLL_MAX_OFFSET 0x444477#define PSOC_EMMC_PLL_SECTION 0x1000478#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull479#define PSOC_MME_PLL_MAX_OFFSET 0x444480#define PSOC_MME_PLL_SECTION 0x1000481#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull482#define PSOC_PCI_PLL_MAX_OFFSET 0x444483#define PSOC_PCI_PLL_SECTION 0x6000484#define mmPSOC_PWM0_BASE 0x7FFCC78000ull485#define PSOC_PWM0_MAX_OFFSET 0x58486#define PSOC_PWM0_SECTION 0x1000487#define mmPSOC_PWM1_BASE 0x7FFCC79000ull488#define PSOC_PWM1_MAX_OFFSET 0x58489#define PSOC_PWM1_SECTION 0x1000490#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull491#define PSOC_PWM2_MAX_OFFSET 0x58492#define PSOC_PWM2_SECTION 0x1000493#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull494#define PSOC_PWM3_MAX_OFFSET 0x58495#define PSOC_PWM3_SECTION 0x185000496#define mmTPC0_NRTR_BASE 0x7FFCE00000ull497#define TPC0_NRTR_MAX_OFFSET 0x608498#define TPC0_NRTR_SECTION 0x1000499#define mmTPC_PLL_BASE 0x7FFCE01000ull500#define TPC_PLL_MAX_OFFSET 0x444501#define TPC_PLL_SECTION 0x1000502#define mmTPC_THEMAL_SENSOR_BASE 0x7FFCE02000ull503#define TPC_THEMAL_SENSOR_MAX_OFFSET 0xE64504#define TPC_THEMAL_SENSOR_SECTION 0x1000505#define mmTPC_PROCESS_MON_BASE 0x7FFCE03000ull506#define TPC_PROCESS_MON_MAX_OFFSET 0x4507#define TPC_PROCESS_MON_SECTION 0x1000508#define mmTPC0_RD_REGULATOR_BASE 0x7FFCE04000ull509#define TPC0_RD_REGULATOR_MAX_OFFSET 0x74510#define TPC0_RD_REGULATOR_SECTION 0x1000511#define mmTPC0_WR_REGULATOR_BASE 0x7FFCE05000ull512#define TPC0_WR_REGULATOR_MAX_OFFSET 0x74513#define TPC0_WR_REGULATOR_SECTION 0x1000514#define mmTPC0_CFG_BASE 0x7FFCE06000ull515#define TPC0_CFG_MAX_OFFSET 0xE30516#define TPC0_CFG_SECTION 0x2000517#define mmTPC0_QM_BASE 0x7FFCE08000ull518#define TPC0_QM_MAX_OFFSET 0x310519#define TPC0_QM_SECTION 0x1000520#define mmTPC0_CMDQ_BASE 0x7FFCE09000ull521#define TPC0_CMDQ_MAX_OFFSET 0x310522#define TPC0_CMDQ_SECTION 0x37000523#define mmTPC1_RTR_BASE 0x7FFCE40000ull524#define TPC1_RTR_MAX_OFFSET 0x608525#define TPC1_RTR_SECTION 0x4000526#define mmTPC1_WR_REGULATOR_BASE 0x7FFCE44000ull527#define TPC1_WR_REGULATOR_MAX_OFFSET 0x74528#define TPC1_WR_REGULATOR_SECTION 0x1000529#define mmTPC1_RD_REGULATOR_BASE 0x7FFCE45000ull530#define TPC1_RD_REGULATOR_MAX_OFFSET 0x74531#define TPC1_RD_REGULATOR_SECTION 0x1000532#define mmTPC1_CFG_BASE 0x7FFCE46000ull533#define TPC1_CFG_MAX_OFFSET 0xE30534#define TPC1_CFG_SECTION 0x2000535#define mmTPC1_QM_BASE 0x7FFCE48000ull536#define TPC1_QM_MAX_OFFSET 0x310537#define TPC1_QM_SECTION 0x1000538#define mmTPC1_CMDQ_BASE 0x7FFCE49000ull539#define TPC1_CMDQ_MAX_OFFSET 0x310540#define TPC1_CMDQ_SECTION 0x37000541#define mmTPC2_RTR_BASE 0x7FFCE80000ull542#define TPC2_RTR_MAX_OFFSET 0x608543#define TPC2_RTR_SECTION 0x4000544#define mmTPC2_RD_REGULATOR_BASE 0x7FFCE84000ull545#define TPC2_RD_REGULATOR_MAX_OFFSET 0x74546#define TPC2_RD_REGULATOR_SECTION 0x1000547#define mmTPC2_WR_REGULATOR_BASE 0x7FFCE85000ull548#define TPC2_WR_REGULATOR_MAX_OFFSET 0x74549#define TPC2_WR_REGULATOR_SECTION 0x1000550#define mmTPC2_CFG_BASE 0x7FFCE86000ull551#define TPC2_CFG_MAX_OFFSET 0xE30552#define TPC2_CFG_SECTION 0x2000553#define mmTPC2_QM_BASE 0x7FFCE88000ull554#define TPC2_QM_MAX_OFFSET 0x310555#define TPC2_QM_SECTION 0x1000556#define mmTPC2_CMDQ_BASE 0x7FFCE89000ull557#define TPC2_CMDQ_MAX_OFFSET 0x310558#define TPC2_CMDQ_SECTION 0x37000559#define mmTPC3_RTR_BASE 0x7FFCEC0000ull560#define TPC3_RTR_MAX_OFFSET 0x608561#define TPC3_RTR_SECTION 0x4000562#define mmTPC3_RD_REGULATOR_BASE 0x7FFCEC4000ull563#define TPC3_RD_REGULATOR_MAX_OFFSET 0x74564#define TPC3_RD_REGULATOR_SECTION 0x1000565#define mmTPC3_WR_REGULATOR_BASE 0x7FFCEC5000ull566#define TPC3_WR_REGULATOR_MAX_OFFSET 0x74567#define TPC3_WR_REGULATOR_SECTION 0x1000568#define mmTPC3_CFG_BASE 0x7FFCEC6000ull569#define TPC3_CFG_MAX_OFFSET 0xE30570#define TPC3_CFG_SECTION 0x2000571#define mmTPC3_QM_BASE 0x7FFCEC8000ull572#define TPC3_QM_MAX_OFFSET 0x310573#define TPC3_QM_SECTION 0x1000574#define mmTPC3_CMDQ_BASE 0x7FFCEC9000ull575#define TPC3_CMDQ_MAX_OFFSET 0x310576#define TPC3_CMDQ_SECTION 0x37000577#define mmTPC4_RTR_BASE 0x7FFCF00000ull578#define TPC4_RTR_MAX_OFFSET 0x608579#define TPC4_RTR_SECTION 0x4000580#define mmTPC4_RD_REGULATOR_BASE 0x7FFCF04000ull581#define TPC4_RD_REGULATOR_MAX_OFFSET 0x74582#define TPC4_RD_REGULATOR_SECTION 0x1000583#define mmTPC4_WR_REGULATOR_BASE 0x7FFCF05000ull584#define TPC4_WR_REGULATOR_MAX_OFFSET 0x74585#define TPC4_WR_REGULATOR_SECTION 0x1000586#define mmTPC4_CFG_BASE 0x7FFCF06000ull587#define TPC4_CFG_MAX_OFFSET 0xE30588#define TPC4_CFG_SECTION 0x2000589#define mmTPC4_QM_BASE 0x7FFCF08000ull590#define TPC4_QM_MAX_OFFSET 0x310591#define TPC4_QM_SECTION 0x1000592#define mmTPC4_CMDQ_BASE 0x7FFCF09000ull593#define TPC4_CMDQ_MAX_OFFSET 0x310594#define TPC4_CMDQ_SECTION 0x37000595#define mmTPC5_RTR_BASE 0x7FFCF40000ull596#define TPC5_RTR_MAX_OFFSET 0x608597#define TPC5_RTR_SECTION 0x4000598#define mmTPC5_RD_REGULATOR_BASE 0x7FFCF44000ull599#define TPC5_RD_REGULATOR_MAX_OFFSET 0x74600#define TPC5_RD_REGULATOR_SECTION 0x1000601#define mmTPC5_WR_REGULATOR_BASE 0x7FFCF45000ull602#define TPC5_WR_REGULATOR_MAX_OFFSET 0x74603#define TPC5_WR_REGULATOR_SECTION 0x1000604#define mmTPC5_CFG_BASE 0x7FFCF46000ull605#define TPC5_CFG_MAX_OFFSET 0xE30606#define TPC5_CFG_SECTION 0x2000607#define mmTPC5_QM_BASE 0x7FFCF48000ull608#define TPC5_QM_MAX_OFFSET 0x310609#define TPC5_QM_SECTION 0x1000610#define mmTPC5_CMDQ_BASE 0x7FFCF49000ull611#define TPC5_CMDQ_MAX_OFFSET 0x310612#define TPC5_CMDQ_SECTION 0x37000613#define mmTPC6_RTR_BASE 0x7FFCF80000ull614#define TPC6_RTR_MAX_OFFSET 0x608615#define TPC6_RTR_SECTION 0x4000616#define mmTPC6_RD_REGULATOR_BASE 0x7FFCF84000ull617#define TPC6_RD_REGULATOR_MAX_OFFSET 0x74618#define TPC6_RD_REGULATOR_SECTION 0x1000619#define mmTPC6_WR_REGULATOR_BASE 0x7FFCF85000ull620#define TPC6_WR_REGULATOR_MAX_OFFSET 0x74621#define TPC6_WR_REGULATOR_SECTION 0x1000622#define mmTPC6_CFG_BASE 0x7FFCF86000ull623#define TPC6_CFG_MAX_OFFSET 0xE30624#define TPC6_CFG_SECTION 0x2000625#define mmTPC6_QM_BASE 0x7FFCF88000ull626#define TPC6_QM_MAX_OFFSET 0x310627#define TPC6_QM_SECTION 0x1000628#define mmTPC6_CMDQ_BASE 0x7FFCF89000ull629#define TPC6_CMDQ_MAX_OFFSET 0x310630#define TPC6_CMDQ_SECTION 0x37000631#define mmTPC7_NRTR_BASE 0x7FFCFC0000ull632#define TPC7_NRTR_MAX_OFFSET 0x608633#define TPC7_NRTR_SECTION 0x4000634#define mmTPC7_RD_REGULATOR_BASE 0x7FFCFC4000ull635#define TPC7_RD_REGULATOR_MAX_OFFSET 0x74636#define TPC7_RD_REGULATOR_SECTION 0x1000637#define mmTPC7_WR_REGULATOR_BASE 0x7FFCFC5000ull638#define TPC7_WR_REGULATOR_MAX_OFFSET 0x74639#define TPC7_WR_REGULATOR_SECTION 0x1000640#define mmTPC7_CFG_BASE 0x7FFCFC6000ull641#define TPC7_CFG_MAX_OFFSET 0xE30642#define TPC7_CFG_SECTION 0x2000643#define mmTPC7_QM_BASE 0x7FFCFC8000ull644#define TPC7_QM_MAX_OFFSET 0x310645#define TPC7_QM_SECTION 0x1000646#define mmTPC7_CMDQ_BASE 0x7FFCFC9000ull647#define TPC7_CMDQ_MAX_OFFSET 0x310648#define TPC7_CMDQ_SECTION 0x1037000649#define mmMME_TOP_TABLE_BASE 0x7FFE000000ull650#define MME_TOP_TABLE_MAX_OFFSET 0x1000651#define MME_TOP_TABLE_SECTION 0x1000652#define mmMME0_RTR_FUNNEL_BASE 0x7FFE001000ull653#define MME0_RTR_FUNNEL_MAX_OFFSET 0x1000654#define MME0_RTR_FUNNEL_SECTION 0x40000655#define mmMME1_RTR_FUNNEL_BASE 0x7FFE041000ull656#define MME1_RTR_FUNNEL_MAX_OFFSET 0x1000657#define MME1_RTR_FUNNEL_SECTION 0x1000658#define mmMME1_SBA_STM_BASE 0x7FFE042000ull659#define MME1_SBA_STM_MAX_OFFSET 0x1000660#define MME1_SBA_STM_SECTION 0x1000661#define mmMME1_SBA_CTI_BASE 0x7FFE043000ull662#define MME1_SBA_CTI_MAX_OFFSET 0x1000663#define MME1_SBA_CTI_SECTION 0x1000664#define mmMME1_SBA_ETF_BASE 0x7FFE044000ull665#define MME1_SBA_ETF_MAX_OFFSET 0x1000666#define MME1_SBA_ETF_SECTION 0x1000667#define mmMME1_SBA_SPMU_BASE 0x7FFE045000ull668#define MME1_SBA_SPMU_MAX_OFFSET 0x1000669#define MME1_SBA_SPMU_SECTION 0x1000670#define mmMME1_SBA_CTI0_BASE 0x7FFE046000ull671#define MME1_SBA_CTI0_MAX_OFFSET 0x1000672#define MME1_SBA_CTI0_SECTION 0x1000673#define mmMME1_SBA_CTI1_BASE 0x7FFE047000ull674#define MME1_SBA_CTI1_MAX_OFFSET 0x1000675#define MME1_SBA_CTI1_SECTION 0x1000676#define mmMME1_SBA_BMON0_BASE 0x7FFE048000ull677#define MME1_SBA_BMON0_MAX_OFFSET 0x1000678#define MME1_SBA_BMON0_SECTION 0x1000679#define mmMME1_SBA_BMON1_BASE 0x7FFE049000ull680#define MME1_SBA_BMON1_MAX_OFFSET 0x1000681#define MME1_SBA_BMON1_SECTION 0x38000682#define mmMME2_RTR_FUNNEL_BASE 0x7FFE081000ull683#define MME2_RTR_FUNNEL_MAX_OFFSET 0x1000684#define MME2_RTR_FUNNEL_SECTION 0x40000685#define mmMME3_RTR_FUNNEL_BASE 0x7FFE0C1000ull686#define MME3_RTR_FUNNEL_MAX_OFFSET 0x1000687#define MME3_RTR_FUNNEL_SECTION 0x1000688#define mmMME3_SBB_STM_BASE 0x7FFE0C2000ull689#define MME3_SBB_STM_MAX_OFFSET 0x1000690#define MME3_SBB_STM_SECTION 0x1000691#define mmMME3_SBB_CTI_BASE 0x7FFE0C3000ull692#define MME3_SBB_CTI_MAX_OFFSET 0x1000693#define MME3_SBB_CTI_SECTION 0x1000694#define mmMME3_SBB_ETF_BASE 0x7FFE0C4000ull695#define MME3_SBB_ETF_MAX_OFFSET 0x1000696#define MME3_SBB_ETF_SECTION 0x1000697#define mmMME3_SBB_SPMU_BASE 0x7FFE0C5000ull698#define MME3_SBB_SPMU_MAX_OFFSET 0x1000699#define MME3_SBB_SPMU_SECTION 0x1000700#define mmMME3_SBB_CTI0_BASE 0x7FFE0C6000ull701#define MME3_SBB_CTI0_MAX_OFFSET 0x1000702#define MME3_SBB_CTI0_SECTION 0x1000703#define mmMME3_SBB_CTI1_BASE 0x7FFE0C7000ull704#define MME3_SBB_CTI1_MAX_OFFSET 0x1000705#define MME3_SBB_CTI1_SECTION 0x1000706#define mmMME3_SBB_BMON0_BASE 0x7FFE0C8000ull707#define MME3_SBB_BMON0_MAX_OFFSET 0x1000708#define MME3_SBB_BMON0_SECTION 0x1000709#define mmMME3_SBB_BMON1_BASE 0x7FFE0C9000ull710#define MME3_SBB_BMON1_MAX_OFFSET 0x1000711#define MME3_SBB_BMON1_SECTION 0x38000712#define mmMME4_RTR_FUNNEL_BASE 0x7FFE101000ull713#define MME4_RTR_FUNNEL_MAX_OFFSET 0x1000714#define MME4_RTR_FUNNEL_SECTION 0x1000715#define mmMME4_WACS_STM_BASE 0x7FFE102000ull716#define MME4_WACS_STM_MAX_OFFSET 0x1000717#define MME4_WACS_STM_SECTION 0x1000718#define mmMME4_WACS_CTI_BASE 0x7FFE103000ull719#define MME4_WACS_CTI_MAX_OFFSET 0x1000720#define MME4_WACS_CTI_SECTION 0x1000721#define mmMME4_WACS_ETF_BASE 0x7FFE104000ull722#define MME4_WACS_ETF_MAX_OFFSET 0x1000723#define MME4_WACS_ETF_SECTION 0x1000724#define mmMME4_WACS_SPMU_BASE 0x7FFE105000ull725#define MME4_WACS_SPMU_MAX_OFFSET 0x1000726#define MME4_WACS_SPMU_SECTION 0x1000727#define mmMME4_WACS_CTI0_BASE 0x7FFE106000ull728#define MME4_WACS_CTI0_MAX_OFFSET 0x1000729#define MME4_WACS_CTI0_SECTION 0x1000730#define mmMME4_WACS_CTI1_BASE 0x7FFE107000ull731#define MME4_WACS_CTI1_MAX_OFFSET 0x1000732#define MME4_WACS_CTI1_SECTION 0x1000733#define mmMME4_WACS_BMON0_BASE 0x7FFE108000ull734#define MME4_WACS_BMON0_MAX_OFFSET 0x1000735#define MME4_WACS_BMON0_SECTION 0x1000736#define mmMME4_WACS_BMON1_BASE 0x7FFE109000ull737#define MME4_WACS_BMON1_MAX_OFFSET 0x1000738#define MME4_WACS_BMON1_SECTION 0x1000739#define mmMME4_WACS_BMON2_BASE 0x7FFE10A000ull740#define MME4_WACS_BMON2_MAX_OFFSET 0x1000741#define MME4_WACS_BMON2_SECTION 0x1000742#define mmMME4_WACS_BMON3_BASE 0x7FFE10B000ull743#define MME4_WACS_BMON3_MAX_OFFSET 0x1000744#define MME4_WACS_BMON3_SECTION 0x1000745#define mmMME4_WACS_BMON4_BASE 0x7FFE10C000ull746#define MME4_WACS_BMON4_MAX_OFFSET 0x1000747#define MME4_WACS_BMON4_SECTION 0x1000748#define mmMME4_WACS_BMON5_BASE 0x7FFE10D000ull749#define MME4_WACS_BMON5_MAX_OFFSET 0x1000750#define MME4_WACS_BMON5_SECTION 0x1000751#define mmMME4_WACS_BMON6_BASE 0x7FFE10E000ull752#define MME4_WACS_BMON6_MAX_OFFSET 0x1000753#define MME4_WACS_BMON6_SECTION 0x4000754#define mmMME4_WACS2_STM_BASE 0x7FFE112000ull755#define MME4_WACS2_STM_MAX_OFFSET 0x1000756#define MME4_WACS2_STM_SECTION 0x1000757#define mmMME4_WACS2_CTI_BASE 0x7FFE113000ull758#define MME4_WACS2_CTI_MAX_OFFSET 0x1000759#define MME4_WACS2_CTI_SECTION 0x1000760#define mmMME4_WACS2_ETF_BASE 0x7FFE114000ull761#define MME4_WACS2_ETF_MAX_OFFSET 0x1000762#define MME4_WACS2_ETF_SECTION 0x1000763#define mmMME4_WACS2_SPMU_BASE 0x7FFE115000ull764#define MME4_WACS2_SPMU_MAX_OFFSET 0x1000765#define MME4_WACS2_SPMU_SECTION 0x1000766#define mmMME4_WACS2_CTI0_BASE 0x7FFE116000ull767#define MME4_WACS2_CTI0_MAX_OFFSET 0x1000768#define MME4_WACS2_CTI0_SECTION 0x1000769#define mmMME4_WACS2_CTI1_BASE 0x7FFE117000ull770#define MME4_WACS2_CTI1_MAX_OFFSET 0x1000771#define MME4_WACS2_CTI1_SECTION 0x1000772#define mmMME4_WACS2_BMON0_BASE 0x7FFE118000ull773#define MME4_WACS2_BMON0_MAX_OFFSET 0x1000774#define MME4_WACS2_BMON0_SECTION 0x1000775#define mmMME4_WACS2_BMON1_BASE 0x7FFE119000ull776#define MME4_WACS2_BMON1_MAX_OFFSET 0x1000777#define MME4_WACS2_BMON1_SECTION 0x1000778#define mmMME4_WACS2_BMON2_BASE 0x7FFE11A000ull779#define MME4_WACS2_BMON2_MAX_OFFSET 0x1000780#define MME4_WACS2_BMON2_SECTION 0x27000781#define mmMME5_RTR_FUNNEL_BASE 0x7FFE141000ull782#define MME5_RTR_FUNNEL_MAX_OFFSET 0x1000783#define MME5_RTR_FUNNEL_SECTION 0x2BF000784#define mmDMA_ROM_TABLE_BASE 0x7FFE400000ull785#define DMA_ROM_TABLE_MAX_OFFSET 0x1000786#define DMA_ROM_TABLE_SECTION 0x1000787#define mmDMA_CH_0_CS_STM_BASE 0x7FFE401000ull788#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000789#define DMA_CH_0_CS_STM_SECTION 0x1000790#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE402000ull791#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000792#define DMA_CH_0_CS_CTI_SECTION 0x1000793#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE403000ull794#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000795#define DMA_CH_0_CS_ETF_SECTION 0x1000796#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE404000ull797#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000798#define DMA_CH_0_CS_SPMU_SECTION 0x1000799#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE405000ull800#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000801#define DMA_CH_0_BMON_CTI_SECTION 0x1000802#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE406000ull803#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000804#define DMA_CH_0_USER_CTI_SECTION 0x1000805#define mmDMA_CH_0_BMON_0_BASE 0x7FFE407000ull806#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000807#define DMA_CH_0_BMON_0_SECTION 0x1000808#define mmDMA_CH_0_BMON_1_BASE 0x7FFE408000ull809#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000810#define DMA_CH_0_BMON_1_SECTION 0x9000811#define mmDMA_CH_1_CS_STM_BASE 0x7FFE411000ull812#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000813#define DMA_CH_1_CS_STM_SECTION 0x1000814#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE412000ull815#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000816#define DMA_CH_1_CS_CTI_SECTION 0x1000817#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE413000ull818#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000819#define DMA_CH_1_CS_ETF_SECTION 0x1000820#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE414000ull821#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000822#define DMA_CH_1_CS_SPMU_SECTION 0x1000823#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE415000ull824#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000825#define DMA_CH_1_BMON_CTI_SECTION 0x1000826#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE416000ull827#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000828#define DMA_CH_1_USER_CTI_SECTION 0x1000829#define mmDMA_CH_1_BMON_0_BASE 0x7FFE417000ull830#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000831#define DMA_CH_1_BMON_0_SECTION 0x1000832#define mmDMA_CH_1_BMON_1_BASE 0x7FFE418000ull833#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000834#define DMA_CH_1_BMON_1_SECTION 0x9000835#define mmDMA_CH_2_CS_STM_BASE 0x7FFE421000ull836#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000837#define DMA_CH_2_CS_STM_SECTION 0x1000838#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE422000ull839#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000840#define DMA_CH_2_CS_CTI_SECTION 0x1000841#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE423000ull842#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000843#define DMA_CH_2_CS_ETF_SECTION 0x1000844#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE424000ull845#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000846#define DMA_CH_2_CS_SPMU_SECTION 0x1000847#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE425000ull848#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000849#define DMA_CH_2_BMON_CTI_SECTION 0x1000850#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE426000ull851#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000852#define DMA_CH_2_USER_CTI_SECTION 0x1000853#define mmDMA_CH_2_BMON_0_BASE 0x7FFE427000ull854#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000855#define DMA_CH_2_BMON_0_SECTION 0x1000856#define mmDMA_CH_2_BMON_1_BASE 0x7FFE428000ull857#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000858#define DMA_CH_2_BMON_1_SECTION 0x9000859#define mmDMA_CH_3_CS_STM_BASE 0x7FFE431000ull860#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000861#define DMA_CH_3_CS_STM_SECTION 0x1000862#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE432000ull863#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000864#define DMA_CH_3_CS_CTI_SECTION 0x1000865#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE433000ull866#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000867#define DMA_CH_3_CS_ETF_SECTION 0x1000868#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE434000ull869#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000870#define DMA_CH_3_CS_SPMU_SECTION 0x1000871#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE435000ull872#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000873#define DMA_CH_3_BMON_CTI_SECTION 0x1000874#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE436000ull875#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000876#define DMA_CH_3_USER_CTI_SECTION 0x1000877#define mmDMA_CH_3_BMON_0_BASE 0x7FFE437000ull878#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000879#define DMA_CH_3_BMON_0_SECTION 0x1000880#define mmDMA_CH_3_BMON_1_BASE 0x7FFE438000ull881#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000882#define DMA_CH_3_BMON_1_SECTION 0x9000883#define mmDMA_CH_4_CS_STM_BASE 0x7FFE441000ull884#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000885#define DMA_CH_4_CS_STM_SECTION 0x1000886#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE442000ull887#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000888#define DMA_CH_4_CS_CTI_SECTION 0x1000889#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE443000ull890#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000891#define DMA_CH_4_CS_ETF_SECTION 0x1000892#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE444000ull893#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000894#define DMA_CH_4_CS_SPMU_SECTION 0x1000895#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE445000ull896#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000897#define DMA_CH_4_BMON_CTI_SECTION 0x1000898#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE446000ull899#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000900#define DMA_CH_4_USER_CTI_SECTION 0x1000901#define mmDMA_CH_4_BMON_0_BASE 0x7FFE447000ull902#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000903#define DMA_CH_4_BMON_0_SECTION 0x1000904#define mmDMA_CH_4_BMON_1_BASE 0x7FFE448000ull905#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000906#define DMA_CH_4_BMON_1_SECTION 0x8000907#define mmDMA_CH_FUNNEL_6_1_BASE 0x7FFE450000ull908#define DMA_CH_FUNNEL_6_1_MAX_OFFSET 0x1000909#define DMA_CH_FUNNEL_6_1_SECTION 0x11000910#define mmDMA_MACRO_CS_STM_BASE 0x7FFE461000ull911#define DMA_MACRO_CS_STM_MAX_OFFSET 0x1000912#define DMA_MACRO_CS_STM_SECTION 0x1000913#define mmDMA_MACRO_CS_CTI_BASE 0x7FFE462000ull914#define DMA_MACRO_CS_CTI_MAX_OFFSET 0x1000915#define DMA_MACRO_CS_CTI_SECTION 0x1000916#define mmDMA_MACRO_CS_ETF_BASE 0x7FFE463000ull917#define DMA_MACRO_CS_ETF_MAX_OFFSET 0x1000918#define DMA_MACRO_CS_ETF_SECTION 0x1000919#define mmDMA_MACRO_CS_SPMU_BASE 0x7FFE464000ull920#define DMA_MACRO_CS_SPMU_MAX_OFFSET 0x1000921#define DMA_MACRO_CS_SPMU_SECTION 0x1000922#define mmDMA_MACRO_BMON_CTI_BASE 0x7FFE465000ull923#define DMA_MACRO_BMON_CTI_MAX_OFFSET 0x1000924#define DMA_MACRO_BMON_CTI_SECTION 0x1000925#define mmDMA_MACRO_USER_CTI_BASE 0x7FFE466000ull926#define DMA_MACRO_USER_CTI_MAX_OFFSET 0x1000927#define DMA_MACRO_USER_CTI_SECTION 0x1000928#define mmDMA_MACRO_BMON_0_BASE 0x7FFE467000ull929#define DMA_MACRO_BMON_0_MAX_OFFSET 0x1000930#define DMA_MACRO_BMON_0_SECTION 0x1000931#define mmDMA_MACRO_BMON_1_BASE 0x7FFE468000ull932#define DMA_MACRO_BMON_1_MAX_OFFSET 0x1000933#define DMA_MACRO_BMON_1_SECTION 0x1000934#define mmDMA_MACRO_BMON_2_BASE 0x7FFE469000ull935#define DMA_MACRO_BMON_2_MAX_OFFSET 0x1000936#define DMA_MACRO_BMON_2_SECTION 0x1000937#define mmDMA_MACRO_BMON_3_BASE 0x7FFE46A000ull938#define DMA_MACRO_BMON_3_MAX_OFFSET 0x1000939#define DMA_MACRO_BMON_3_SECTION 0x1000940#define mmDMA_MACRO_BMON_4_BASE 0x7FFE46B000ull941#define DMA_MACRO_BMON_4_MAX_OFFSET 0x1000942#define DMA_MACRO_BMON_4_SECTION 0x1000943#define mmDMA_MACRO_BMON_5_BASE 0x7FFE46C000ull944#define DMA_MACRO_BMON_5_MAX_OFFSET 0x1000945#define DMA_MACRO_BMON_5_SECTION 0x1000946#define mmDMA_MACRO_BMON_6_BASE 0x7FFE46D000ull947#define DMA_MACRO_BMON_6_MAX_OFFSET 0x1000948#define DMA_MACRO_BMON_6_SECTION 0x1000949#define mmDMA_MACRO_BMON_7_BASE 0x7FFE46E000ull950#define DMA_MACRO_BMON_7_MAX_OFFSET 0x1000951#define DMA_MACRO_BMON_7_SECTION 0x2000952#define mmDMA_MACRO_FUNNEL_3_1_BASE 0x7FFE470000ull953#define DMA_MACRO_FUNNEL_3_1_MAX_OFFSET 0x1000954#define DMA_MACRO_FUNNEL_3_1_SECTION 0x10000955#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull956#define CPU_ROM_TABLE_MAX_OFFSET 0x1000957#define CPU_ROM_TABLE_SECTION 0x1000958#define mmCPU_ETF_0_BASE 0x7FFE481000ull959#define CPU_ETF_0_MAX_OFFSET 0x1000960#define CPU_ETF_0_SECTION 0x1000961#define mmCPU_ETF_1_BASE 0x7FFE482000ull962#define CPU_ETF_1_MAX_OFFSET 0x1000963#define CPU_ETF_1_SECTION 0x2000964#define mmCPU_CTI_BASE 0x7FFE484000ull965#define CPU_CTI_MAX_OFFSET 0x1000966#define CPU_CTI_SECTION 0x1000967#define mmCPU_FUNNEL_BASE 0x7FFE485000ull968#define CPU_FUNNEL_MAX_OFFSET 0x1000969#define CPU_FUNNEL_SECTION 0x1000970#define mmCPU_STM_BASE 0x7FFE486000ull971#define CPU_STM_MAX_OFFSET 0x1000972#define CPU_STM_SECTION 0x1000973#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull974#define CPU_CTI_TRACE_MAX_OFFSET 0x1000975#define CPU_CTI_TRACE_SECTION 0x1000976#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull977#define CPU_ETF_TRACE_MAX_OFFSET 0x1000978#define CPU_ETF_TRACE_SECTION 0x1000979#define mmCPU_WR_BMON_BASE 0x7FFE489000ull980#define CPU_WR_BMON_MAX_OFFSET 0x1000981#define CPU_WR_BMON_SECTION 0x1000982#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull983#define CPU_RD_BMON_MAX_OFFSET 0x1000984#define CPU_RD_BMON_SECTION 0x37000985#define mmMMU_CS_STM_BASE 0x7FFE4C1000ull986#define MMU_CS_STM_MAX_OFFSET 0x1000987#define MMU_CS_STM_SECTION 0x1000988#define mmMMU_CS_CTI_BASE 0x7FFE4C2000ull989#define MMU_CS_CTI_MAX_OFFSET 0x1000990#define MMU_CS_CTI_SECTION 0x1000991#define mmMMU_CS_ETF_BASE 0x7FFE4C3000ull992#define MMU_CS_ETF_MAX_OFFSET 0x1000993#define MMU_CS_ETF_SECTION 0x1000994#define mmMMU_CS_SPMU_BASE 0x7FFE4C4000ull995#define MMU_CS_SPMU_MAX_OFFSET 0x1000996#define MMU_CS_SPMU_SECTION 0x1000997#define mmMMU_BMON_CTI_BASE 0x7FFE4C5000ull998#define MMU_BMON_CTI_MAX_OFFSET 0x1000999#define MMU_BMON_CTI_SECTION 0x10001000#define mmMMU_USER_CTI_BASE 0x7FFE4C6000ull1001#define MMU_USER_CTI_MAX_OFFSET 0x10001002#define MMU_USER_CTI_SECTION 0x10001003#define mmMMU_BMON_0_BASE 0x7FFE4C7000ull1004#define MMU_BMON_0_MAX_OFFSET 0x10001005#define MMU_BMON_0_SECTION 0x10001006#define mmMMU_BMON_1_BASE 0x7FFE4C8000ull1007#define MMU_BMON_1_MAX_OFFSET 0x10001008#define MMU_BMON_1_SECTION 0x3380001009#define mmCA53_BASE 0x7FFE800000ull1010#define CA53_MAX_OFFSET 0x10001011#define CA53_SECTION 0x4000001012#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull1013#define PCI_ROM_TABLE_MAX_OFFSET 0x10001014#define PCI_ROM_TABLE_SECTION 0x10001015#define mmPCIE_STM_BASE 0x7FFEC01000ull1016#define PCIE_STM_MAX_OFFSET 0x10001017#define PCIE_STM_SECTION 0x10001018#define mmPCIE_ETF_BASE 0x7FFEC02000ull1019#define PCIE_ETF_MAX_OFFSET 0x10001020#define PCIE_ETF_SECTION 0x10001021#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull1022#define PCIE_CTI_0_MAX_OFFSET 0x10001023#define PCIE_CTI_0_SECTION 0x10001024#define mmPCIE_SPMU_BASE 0x7FFEC04000ull1025#define PCIE_SPMU_MAX_OFFSET 0x10001026#define PCIE_SPMU_SECTION 0x10001027#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull1028#define PCIE_CTI_1_MAX_OFFSET 0x10001029#define PCIE_CTI_1_SECTION 0x10001030#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull1031#define PCIE_FUNNEL_MAX_OFFSET 0x10001032#define PCIE_FUNNEL_SECTION 0x10001033#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull1034#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x10001035#define PCIE_BMON_MSTR_WR_SECTION 0x10001036#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull1037#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x10001038#define PCIE_BMON_MSTR_RD_SECTION 0x10001039#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull1040#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x10001041#define PCIE_BMON_SLV_WR_SECTION 0x10001042#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull1043#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x10001044#define PCIE_BMON_SLV_RD_SECTION 0x360001045#define mmPSOC_CTI_BASE 0x7FFEC40000ull1046#define PSOC_CTI_MAX_OFFSET 0x10001047#define PSOC_CTI_SECTION 0x10001048#define mmPSOC_STM_BASE 0x7FFEC41000ull1049#define PSOC_STM_MAX_OFFSET 0x10001050#define PSOC_STM_SECTION 0x10001051#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull1052#define PSOC_FUNNEL_MAX_OFFSET 0x10001053#define PSOC_FUNNEL_SECTION 0x10001054#define mmPSOC_ETR_BASE 0x7FFEC43000ull1055#define PSOC_ETR_MAX_OFFSET 0x10001056#define PSOC_ETR_SECTION 0x10001057#define mmPSOC_ETF_BASE 0x7FFEC44000ull1058#define PSOC_ETF_MAX_OFFSET 0x10001059#define PSOC_ETF_SECTION 0x10001060#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull1061#define PSOC_TS_CTI_MAX_OFFSET 0x10001062#define PSOC_TS_CTI_SECTION 0xB0001063#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull1064#define TOP_ROM_TABLE_MAX_OFFSET 0x10001065#define TOP_ROM_TABLE_SECTION 0x1F00001066#define mmTPC1_RTR_FUNNEL_BASE 0x7FFEE40000ull1067#define TPC1_RTR_FUNNEL_MAX_OFFSET 0x10001068#define TPC1_RTR_FUNNEL_SECTION 0x400001069#define mmTPC2_RTR_FUNNEL_BASE 0x7FFEE80000ull1070#define TPC2_RTR_FUNNEL_MAX_OFFSET 0x10001071#define TPC2_RTR_FUNNEL_SECTION 0x400001072#define mmTPC3_RTR_FUNNEL_BASE 0x7FFEEC0000ull1073#define TPC3_RTR_FUNNEL_MAX_OFFSET 0x10001074#define TPC3_RTR_FUNNEL_SECTION 0x400001075#define mmTPC4_RTR_FUNNEL_BASE 0x7FFEF00000ull1076#define TPC4_RTR_FUNNEL_MAX_OFFSET 0x10001077#define TPC4_RTR_FUNNEL_SECTION 0x400001078#define mmTPC5_RTR_FUNNEL_BASE 0x7FFEF40000ull1079#define TPC5_RTR_FUNNEL_MAX_OFFSET 0x10001080#define TPC5_RTR_FUNNEL_SECTION 0x400001081#define mmTPC6_RTR_FUNNEL_BASE 0x7FFEF80000ull1082#define TPC6_RTR_FUNNEL_MAX_OFFSET 0x10001083#define TPC6_RTR_FUNNEL_SECTION 0x810001084#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull1085#define TPC0_EML_SPMU_MAX_OFFSET 0x10001086#define TPC0_EML_SPMU_SECTION 0x10001087#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull1088#define TPC0_EML_ETF_MAX_OFFSET 0x10001089#define TPC0_EML_ETF_SECTION 0x10001090#define mmTPC0_EML_STM_BASE 0x7FFF003000ull1091#define TPC0_EML_STM_MAX_OFFSET 0x10001092#define TPC0_EML_STM_SECTION 0x10001093#define mmTPC0_EML_ETM_R4_BASE 0x7FFF004000ull1094#define TPC0_EML_ETM_R4_MAX_OFFSET 0x01095#define TPC0_EML_ETM_R4_SECTION 0x10001096#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull1097#define TPC0_EML_CTI_MAX_OFFSET 0x10001098#define TPC0_EML_CTI_SECTION 0x10001099#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull1100#define TPC0_EML_FUNNEL_MAX_OFFSET 0x10001101#define TPC0_EML_FUNNEL_SECTION 0x10001102#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull1103#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x10001104#define TPC0_EML_BUSMON_0_SECTION 0x10001105#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull1106#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x10001107#define TPC0_EML_BUSMON_1_SECTION 0x10001108#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull1109#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x10001110#define TPC0_EML_BUSMON_2_SECTION 0x10001111#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull1112#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x10001113#define TPC0_EML_BUSMON_3_SECTION 0x360001114#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull1115#define TPC0_EML_CFG_MAX_OFFSET 0x3381116#define TPC0_EML_CFG_SECTION 0x1BF0001117#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull1118#define TPC0_EML_CS_MAX_OFFSET 0x10001119#define TPC0_EML_CS_SECTION 0x20001120#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull1121#define TPC1_EML_SPMU_MAX_OFFSET 0x10001122#define TPC1_EML_SPMU_SECTION 0x10001123#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull1124#define TPC1_EML_ETF_MAX_OFFSET 0x10001125#define TPC1_EML_ETF_SECTION 0x10001126#define mmTPC1_EML_STM_BASE 0x7FFF203000ull1127#define TPC1_EML_STM_MAX_OFFSET 0x10001128#define TPC1_EML_STM_SECTION 0x10001129#define mmTPC1_EML_ETM_R4_BASE 0x7FFF204000ull1130#define TPC1_EML_ETM_R4_MAX_OFFSET 0x01131#define TPC1_EML_ETM_R4_SECTION 0x10001132#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull1133#define TPC1_EML_CTI_MAX_OFFSET 0x10001134#define TPC1_EML_CTI_SECTION 0x10001135#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull1136#define TPC1_EML_FUNNEL_MAX_OFFSET 0x10001137#define TPC1_EML_FUNNEL_SECTION 0x10001138#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull1139#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x10001140#define TPC1_EML_BUSMON_0_SECTION 0x10001141#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull1142#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x10001143#define TPC1_EML_BUSMON_1_SECTION 0x10001144#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull1145#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x10001146#define TPC1_EML_BUSMON_2_SECTION 0x10001147#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull1148#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x10001149#define TPC1_EML_BUSMON_3_SECTION 0x360001150#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull1151#define TPC1_EML_CFG_MAX_OFFSET 0x3381152#define TPC1_EML_CFG_SECTION 0x1BF0001153#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull1154#define TPC1_EML_CS_MAX_OFFSET 0x10001155#define TPC1_EML_CS_SECTION 0x20001156#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull1157#define TPC2_EML_SPMU_MAX_OFFSET 0x10001158#define TPC2_EML_SPMU_SECTION 0x10001159#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull1160#define TPC2_EML_ETF_MAX_OFFSET 0x10001161#define TPC2_EML_ETF_SECTION 0x10001162#define mmTPC2_EML_STM_BASE 0x7FFF403000ull1163#define TPC2_EML_STM_MAX_OFFSET 0x10001164#define TPC2_EML_STM_SECTION 0x10001165#define mmTPC2_EML_ETM_R4_BASE 0x7FFF404000ull1166#define TPC2_EML_ETM_R4_MAX_OFFSET 0x01167#define TPC2_EML_ETM_R4_SECTION 0x10001168#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull1169#define TPC2_EML_CTI_MAX_OFFSET 0x10001170#define TPC2_EML_CTI_SECTION 0x10001171#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull1172#define TPC2_EML_FUNNEL_MAX_OFFSET 0x10001173#define TPC2_EML_FUNNEL_SECTION 0x10001174#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull1175#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x10001176#define TPC2_EML_BUSMON_0_SECTION 0x10001177#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull1178#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x10001179#define TPC2_EML_BUSMON_1_SECTION 0x10001180#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull1181#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x10001182#define TPC2_EML_BUSMON_2_SECTION 0x10001183#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull1184#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x10001185#define TPC2_EML_BUSMON_3_SECTION 0x360001186#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull1187#define TPC2_EML_CFG_MAX_OFFSET 0x3381188#define TPC2_EML_CFG_SECTION 0x1BF0001189#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull1190#define TPC2_EML_CS_MAX_OFFSET 0x10001191#define TPC2_EML_CS_SECTION 0x20001192#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull1193#define TPC3_EML_SPMU_MAX_OFFSET 0x10001194#define TPC3_EML_SPMU_SECTION 0x10001195#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull1196#define TPC3_EML_ETF_MAX_OFFSET 0x10001197#define TPC3_EML_ETF_SECTION 0x10001198#define mmTPC3_EML_STM_BASE 0x7FFF603000ull1199#define TPC3_EML_STM_MAX_OFFSET 0x10001200#define TPC3_EML_STM_SECTION 0x10001201#define mmTPC3_EML_ETM_R4_BASE 0x7FFF604000ull1202#define TPC3_EML_ETM_R4_MAX_OFFSET 0x01203#define TPC3_EML_ETM_R4_SECTION 0x10001204#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull1205#define TPC3_EML_CTI_MAX_OFFSET 0x10001206#define TPC3_EML_CTI_SECTION 0x10001207#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull1208#define TPC3_EML_FUNNEL_MAX_OFFSET 0x10001209#define TPC3_EML_FUNNEL_SECTION 0x10001210#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull1211#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x10001212#define TPC3_EML_BUSMON_0_SECTION 0x10001213#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull1214#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x10001215#define TPC3_EML_BUSMON_1_SECTION 0x10001216#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull1217#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x10001218#define TPC3_EML_BUSMON_2_SECTION 0x10001219#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull1220#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x10001221#define TPC3_EML_BUSMON_3_SECTION 0x360001222#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull1223#define TPC3_EML_CFG_MAX_OFFSET 0x3381224#define TPC3_EML_CFG_SECTION 0x1BF0001225#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull1226#define TPC3_EML_CS_MAX_OFFSET 0x10001227#define TPC3_EML_CS_SECTION 0x20001228#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull1229#define TPC4_EML_SPMU_MAX_OFFSET 0x10001230#define TPC4_EML_SPMU_SECTION 0x10001231#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull1232#define TPC4_EML_ETF_MAX_OFFSET 0x10001233#define TPC4_EML_ETF_SECTION 0x10001234#define mmTPC4_EML_STM_BASE 0x7FFF803000ull1235#define TPC4_EML_STM_MAX_OFFSET 0x10001236#define TPC4_EML_STM_SECTION 0x10001237#define mmTPC4_EML_ETM_R4_BASE 0x7FFF804000ull1238#define TPC4_EML_ETM_R4_MAX_OFFSET 0x01239#define TPC4_EML_ETM_R4_SECTION 0x10001240#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull1241#define TPC4_EML_CTI_MAX_OFFSET 0x10001242#define TPC4_EML_CTI_SECTION 0x10001243#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull1244#define TPC4_EML_FUNNEL_MAX_OFFSET 0x10001245#define TPC4_EML_FUNNEL_SECTION 0x10001246#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull1247#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x10001248#define TPC4_EML_BUSMON_0_SECTION 0x10001249#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull1250#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x10001251#define TPC4_EML_BUSMON_1_SECTION 0x10001252#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull1253#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x10001254#define TPC4_EML_BUSMON_2_SECTION 0x10001255#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull1256#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x10001257#define TPC4_EML_BUSMON_3_SECTION 0x360001258#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull1259#define TPC4_EML_CFG_MAX_OFFSET 0x3381260#define TPC4_EML_CFG_SECTION 0x1BF0001261#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull1262#define TPC4_EML_CS_MAX_OFFSET 0x10001263#define TPC4_EML_CS_SECTION 0x20001264#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull1265#define TPC5_EML_SPMU_MAX_OFFSET 0x10001266#define TPC5_EML_SPMU_SECTION 0x10001267#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull1268#define TPC5_EML_ETF_MAX_OFFSET 0x10001269#define TPC5_EML_ETF_SECTION 0x10001270#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull1271#define TPC5_EML_STM_MAX_OFFSET 0x10001272#define TPC5_EML_STM_SECTION 0x10001273#define mmTPC5_EML_ETM_R4_BASE 0x7FFFA04000ull1274#define TPC5_EML_ETM_R4_MAX_OFFSET 0x01275#define TPC5_EML_ETM_R4_SECTION 0x10001276#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull1277#define TPC5_EML_CTI_MAX_OFFSET 0x10001278#define TPC5_EML_CTI_SECTION 0x10001279#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull1280#define TPC5_EML_FUNNEL_MAX_OFFSET 0x10001281#define TPC5_EML_FUNNEL_SECTION 0x10001282#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull1283#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x10001284#define TPC5_EML_BUSMON_0_SECTION 0x10001285#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull1286#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x10001287#define TPC5_EML_BUSMON_1_SECTION 0x10001288#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull1289#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x10001290#define TPC5_EML_BUSMON_2_SECTION 0x10001291#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull1292#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x10001293#define TPC5_EML_BUSMON_3_SECTION 0x360001294#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull1295#define TPC5_EML_CFG_MAX_OFFSET 0x3381296#define TPC5_EML_CFG_SECTION 0x1BF0001297#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull1298#define TPC5_EML_CS_MAX_OFFSET 0x10001299#define TPC5_EML_CS_SECTION 0x20001300#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull1301#define TPC6_EML_SPMU_MAX_OFFSET 0x10001302#define TPC6_EML_SPMU_SECTION 0x10001303#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull1304#define TPC6_EML_ETF_MAX_OFFSET 0x10001305#define TPC6_EML_ETF_SECTION 0x10001306#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull1307#define TPC6_EML_STM_MAX_OFFSET 0x10001308#define TPC6_EML_STM_SECTION 0x10001309#define mmTPC6_EML_ETM_R4_BASE 0x7FFFC04000ull1310#define TPC6_EML_ETM_R4_MAX_OFFSET 0x01311#define TPC6_EML_ETM_R4_SECTION 0x10001312#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull1313#define TPC6_EML_CTI_MAX_OFFSET 0x10001314#define TPC6_EML_CTI_SECTION 0x10001315#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull1316#define TPC6_EML_FUNNEL_MAX_OFFSET 0x10001317#define TPC6_EML_FUNNEL_SECTION 0x10001318#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull1319#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x10001320#define TPC6_EML_BUSMON_0_SECTION 0x10001321#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull1322#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x10001323#define TPC6_EML_BUSMON_1_SECTION 0x10001324#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull1325#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x10001326#define TPC6_EML_BUSMON_2_SECTION 0x10001327#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull1328#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x10001329#define TPC6_EML_BUSMON_3_SECTION 0x360001330#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull1331#define TPC6_EML_CFG_MAX_OFFSET 0x3381332#define TPC6_EML_CFG_SECTION 0x1BF0001333#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull1334#define TPC6_EML_CS_MAX_OFFSET 0x10001335#define TPC6_EML_CS_SECTION 0x20001336#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull1337#define TPC7_EML_SPMU_MAX_OFFSET 0x10001338#define TPC7_EML_SPMU_SECTION 0x10001339#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull1340#define TPC7_EML_ETF_MAX_OFFSET 0x10001341#define TPC7_EML_ETF_SECTION 0x10001342#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull1343#define TPC7_EML_STM_MAX_OFFSET 0x10001344#define TPC7_EML_STM_SECTION 0x10001345#define mmTPC7_EML_ETM_R4_BASE 0x7FFFE04000ull1346#define TPC7_EML_ETM_R4_MAX_OFFSET 0x01347#define TPC7_EML_ETM_R4_SECTION 0x10001348#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull1349#define TPC7_EML_CTI_MAX_OFFSET 0x10001350#define TPC7_EML_CTI_SECTION 0x10001351#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull1352#define TPC7_EML_FUNNEL_MAX_OFFSET 0x10001353#define TPC7_EML_FUNNEL_SECTION 0x10001354#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull1355#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x10001356#define TPC7_EML_BUSMON_0_SECTION 0x10001357#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull1358#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x10001359#define TPC7_EML_BUSMON_1_SECTION 0x10001360#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull1361#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x10001362#define TPC7_EML_BUSMON_2_SECTION 0x10001363#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull1364#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x10001365#define TPC7_EML_BUSMON_3_SECTION 0x360001366#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull1367#define TPC7_EML_CFG_MAX_OFFSET 0x3381368#define TPC7_EML_CFG_SECTION 0x1BF0001369#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull1370#define TPC7_EML_CS_MAX_OFFSET 0x10001371 1372#endif /* GOYA_BLOCKS_H_ */1373