105 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MC_PLL_REGS_H_14#define ASIC_REG_MC_PLL_REGS_H_15 16/*17 *****************************************18 * MC_PLL (Prototype: PLL)19 *****************************************20 */21 22#define mmMC_PLL_NR 0x4A110023 24#define mmMC_PLL_NF 0x4A110425 26#define mmMC_PLL_OD 0x4A110827 28#define mmMC_PLL_NB 0x4A110C29 30#define mmMC_PLL_CFG 0x4A111031 32#define mmMC_PLL_LOSE_MASK 0x4A112033 34#define mmMC_PLL_LOCK_INTR 0x4A112835 36#define mmMC_PLL_LOCK_BYPASS 0x4A112C37 38#define mmMC_PLL_DATA_CHNG 0x4A113039 40#define mmMC_PLL_RST 0x4A113441 42#define mmMC_PLL_SLIP_WD_CNTR 0x4A115043 44#define mmMC_PLL_DIV_FACTOR_0 0x4A120045 46#define mmMC_PLL_DIV_FACTOR_1 0x4A120447 48#define mmMC_PLL_DIV_FACTOR_2 0x4A120849 50#define mmMC_PLL_DIV_FACTOR_3 0x4A120C51 52#define mmMC_PLL_DIV_FACTOR_CMD_0 0x4A122053 54#define mmMC_PLL_DIV_FACTOR_CMD_1 0x4A122455 56#define mmMC_PLL_DIV_FACTOR_CMD_2 0x4A122857 58#define mmMC_PLL_DIV_FACTOR_CMD_3 0x4A122C59 60#define mmMC_PLL_DIV_SEL_0 0x4A128061 62#define mmMC_PLL_DIV_SEL_1 0x4A128463 64#define mmMC_PLL_DIV_SEL_2 0x4A128865 66#define mmMC_PLL_DIV_SEL_3 0x4A128C67 68#define mmMC_PLL_DIV_EN_0 0x4A12A069 70#define mmMC_PLL_DIV_EN_1 0x4A12A471 72#define mmMC_PLL_DIV_EN_2 0x4A12A873 74#define mmMC_PLL_DIV_EN_3 0x4A12AC75 76#define mmMC_PLL_DIV_FACTOR_BUSY_0 0x4A12C077 78#define mmMC_PLL_DIV_FACTOR_BUSY_1 0x4A12C479 80#define mmMC_PLL_DIV_FACTOR_BUSY_2 0x4A12C881 82#define mmMC_PLL_DIV_FACTOR_BUSY_3 0x4A12CC83 84#define mmMC_PLL_CLK_GATER 0x4A130085 86#define mmMC_PLL_CLK_RLX_0 0x4A131087 88#define mmMC_PLL_CLK_RLX_1 0x4A131489 90#define mmMC_PLL_CLK_RLX_2 0x4A131891 92#define mmMC_PLL_CLK_RLX_3 0x4A131C93 94#define mmMC_PLL_REF_CNTR_PERIOD 0x4A140095 96#define mmMC_PLL_REF_LOW_THRESHOLD 0x4A141097 98#define mmMC_PLL_REF_HIGH_THRESHOLD 0x4A142099 100#define mmMC_PLL_PLL_NOT_STABLE 0x4A1430101 102#define mmMC_PLL_FREQ_CALC_EN 0x4A1440103 104#endif /* ASIC_REG_MC_PLL_REGS_H_ */105