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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME1_RTR_MASKS_H_14#define ASIC_REG_MME1_RTR_MASKS_H_15 16/*17 *****************************************18 * MME1_RTR (Prototype: MME_RTR)19 *****************************************20 */21 22/* MME1_RTR_HBW_RD_RQ_E_ARB */23#define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 024#define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x725#define MME1_RTR_HBW_RD_RQ_E_ARB_S_SHIFT 826#define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x70027#define MME1_RTR_HBW_RD_RQ_E_ARB_N_SHIFT 1628#define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x7000029#define MME1_RTR_HBW_RD_RQ_E_ARB_L_SHIFT 2430#define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x700000031 32/* MME1_RTR_HBW_RD_RQ_W_ARB */33#define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 034#define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x735#define MME1_RTR_HBW_RD_RQ_W_ARB_S_SHIFT 836#define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x70037#define MME1_RTR_HBW_RD_RQ_W_ARB_N_SHIFT 1638#define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x7000039#define MME1_RTR_HBW_RD_RQ_W_ARB_L_SHIFT 2440#define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x700000041 42/* MME1_RTR_HBW_RD_RQ_N_ARB */43#define MME1_RTR_HBW_RD_RQ_N_ARB_W_SHIFT 044#define MME1_RTR_HBW_RD_RQ_N_ARB_W_MASK 0x745#define MME1_RTR_HBW_RD_RQ_N_ARB_E_SHIFT 846#define MME1_RTR_HBW_RD_RQ_N_ARB_E_MASK 0x70047#define MME1_RTR_HBW_RD_RQ_N_ARB_S_SHIFT 1648#define MME1_RTR_HBW_RD_RQ_N_ARB_S_MASK 0x7000049#define MME1_RTR_HBW_RD_RQ_N_ARB_L_SHIFT 2450#define MME1_RTR_HBW_RD_RQ_N_ARB_L_MASK 0x700000051 52/* MME1_RTR_HBW_RD_RQ_S_ARB */53#define MME1_RTR_HBW_RD_RQ_S_ARB_W_SHIFT 054#define MME1_RTR_HBW_RD_RQ_S_ARB_W_MASK 0x755#define MME1_RTR_HBW_RD_RQ_S_ARB_E_SHIFT 856#define MME1_RTR_HBW_RD_RQ_S_ARB_E_MASK 0x70057#define MME1_RTR_HBW_RD_RQ_S_ARB_N_SHIFT 1658#define MME1_RTR_HBW_RD_RQ_S_ARB_N_MASK 0x7000059#define MME1_RTR_HBW_RD_RQ_S_ARB_L_SHIFT 2460#define MME1_RTR_HBW_RD_RQ_S_ARB_L_MASK 0x700000061 62/* MME1_RTR_HBW_RD_RQ_L_ARB */63#define MME1_RTR_HBW_RD_RQ_L_ARB_W_SHIFT 064#define MME1_RTR_HBW_RD_RQ_L_ARB_W_MASK 0x765#define MME1_RTR_HBW_RD_RQ_L_ARB_E_SHIFT 866#define MME1_RTR_HBW_RD_RQ_L_ARB_E_MASK 0x70067#define MME1_RTR_HBW_RD_RQ_L_ARB_S_SHIFT 1668#define MME1_RTR_HBW_RD_RQ_L_ARB_S_MASK 0x7000069#define MME1_RTR_HBW_RD_RQ_L_ARB_N_SHIFT 2470#define MME1_RTR_HBW_RD_RQ_L_ARB_N_MASK 0x700000071 72/* MME1_RTR_HBW_E_ARB_MAX */73#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_SHIFT 074#define MME1_RTR_HBW_E_ARB_MAX_CREDIT_MASK 0x3F75 76/* MME1_RTR_HBW_W_ARB_MAX */77#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_SHIFT 078#define MME1_RTR_HBW_W_ARB_MAX_CREDIT_MASK 0x3F79 80/* MME1_RTR_HBW_N_ARB_MAX */81#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_SHIFT 082#define MME1_RTR_HBW_N_ARB_MAX_CREDIT_MASK 0x3F83 84/* MME1_RTR_HBW_S_ARB_MAX */85#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_SHIFT 086#define MME1_RTR_HBW_S_ARB_MAX_CREDIT_MASK 0x3F87 88/* MME1_RTR_HBW_L_ARB_MAX */89#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_SHIFT 090#define MME1_RTR_HBW_L_ARB_MAX_CREDIT_MASK 0x3F91 92/* MME1_RTR_HBW_RD_RS_MAX_CREDIT */93#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_SHIFT 094#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_MASK 0x3F95#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_SHIFT 896#define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_MASK 0x3F0097 98/* MME1_RTR_HBW_WR_RQ_MAX_CREDIT */99#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_SHIFT 0100#define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_MASK 0x3F101 102/* MME1_RTR_HBW_RD_RQ_MAX_CREDIT */103#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_SHIFT 0104#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_MASK 0x3F105#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_SHIFT 8106#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_MASK 0x3F00107#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_SHIFT 16108#define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_MASK 0x3F0000109 110/* MME1_RTR_HBW_RD_RS_E_ARB */111#define MME1_RTR_HBW_RD_RS_E_ARB_W_SHIFT 0112#define MME1_RTR_HBW_RD_RS_E_ARB_W_MASK 0x7113#define MME1_RTR_HBW_RD_RS_E_ARB_S_SHIFT 8114#define MME1_RTR_HBW_RD_RS_E_ARB_S_MASK 0x700115#define MME1_RTR_HBW_RD_RS_E_ARB_N_SHIFT 16116#define MME1_RTR_HBW_RD_RS_E_ARB_N_MASK 0x70000117#define MME1_RTR_HBW_RD_RS_E_ARB_L_SHIFT 24118#define MME1_RTR_HBW_RD_RS_E_ARB_L_MASK 0x7000000119 120/* MME1_RTR_HBW_RD_RS_W_ARB */121#define MME1_RTR_HBW_RD_RS_W_ARB_E_SHIFT 0122#define MME1_RTR_HBW_RD_RS_W_ARB_E_MASK 0x7123#define MME1_RTR_HBW_RD_RS_W_ARB_S_SHIFT 8124#define MME1_RTR_HBW_RD_RS_W_ARB_S_MASK 0x700125#define MME1_RTR_HBW_RD_RS_W_ARB_N_SHIFT 16126#define MME1_RTR_HBW_RD_RS_W_ARB_N_MASK 0x70000127#define MME1_RTR_HBW_RD_RS_W_ARB_L_SHIFT 24128#define MME1_RTR_HBW_RD_RS_W_ARB_L_MASK 0x7000000129 130/* MME1_RTR_HBW_RD_RS_N_ARB */131#define MME1_RTR_HBW_RD_RS_N_ARB_W_SHIFT 0132#define MME1_RTR_HBW_RD_RS_N_ARB_W_MASK 0x7133#define MME1_RTR_HBW_RD_RS_N_ARB_E_SHIFT 8134#define MME1_RTR_HBW_RD_RS_N_ARB_E_MASK 0x700135#define MME1_RTR_HBW_RD_RS_N_ARB_S_SHIFT 16136#define MME1_RTR_HBW_RD_RS_N_ARB_S_MASK 0x70000137#define MME1_RTR_HBW_RD_RS_N_ARB_L_SHIFT 24138#define MME1_RTR_HBW_RD_RS_N_ARB_L_MASK 0x7000000139 140/* MME1_RTR_HBW_RD_RS_S_ARB */141#define MME1_RTR_HBW_RD_RS_S_ARB_W_SHIFT 0142#define MME1_RTR_HBW_RD_RS_S_ARB_W_MASK 0x7143#define MME1_RTR_HBW_RD_RS_S_ARB_E_SHIFT 8144#define MME1_RTR_HBW_RD_RS_S_ARB_E_MASK 0x700145#define MME1_RTR_HBW_RD_RS_S_ARB_N_SHIFT 16146#define MME1_RTR_HBW_RD_RS_S_ARB_N_MASK 0x70000147#define MME1_RTR_HBW_RD_RS_S_ARB_L_SHIFT 24148#define MME1_RTR_HBW_RD_RS_S_ARB_L_MASK 0x7000000149 150/* MME1_RTR_HBW_RD_RS_L_ARB */151#define MME1_RTR_HBW_RD_RS_L_ARB_W_SHIFT 0152#define MME1_RTR_HBW_RD_RS_L_ARB_W_MASK 0x7153#define MME1_RTR_HBW_RD_RS_L_ARB_E_SHIFT 8154#define MME1_RTR_HBW_RD_RS_L_ARB_E_MASK 0x700155#define MME1_RTR_HBW_RD_RS_L_ARB_S_SHIFT 16156#define MME1_RTR_HBW_RD_RS_L_ARB_S_MASK 0x70000157#define MME1_RTR_HBW_RD_RS_L_ARB_N_SHIFT 24158#define MME1_RTR_HBW_RD_RS_L_ARB_N_MASK 0x7000000159 160/* MME1_RTR_HBW_WR_RQ_E_ARB */161#define MME1_RTR_HBW_WR_RQ_E_ARB_W_SHIFT 0162#define MME1_RTR_HBW_WR_RQ_E_ARB_W_MASK 0x7163#define MME1_RTR_HBW_WR_RQ_E_ARB_S_SHIFT 8164#define MME1_RTR_HBW_WR_RQ_E_ARB_S_MASK 0x700165#define MME1_RTR_HBW_WR_RQ_E_ARB_N_SHIFT 16166#define MME1_RTR_HBW_WR_RQ_E_ARB_N_MASK 0x70000167#define MME1_RTR_HBW_WR_RQ_E_ARB_L_SHIFT 24168#define MME1_RTR_HBW_WR_RQ_E_ARB_L_MASK 0x7000000169 170/* MME1_RTR_HBW_WR_RQ_W_ARB */171#define MME1_RTR_HBW_WR_RQ_W_ARB_E_SHIFT 0172#define MME1_RTR_HBW_WR_RQ_W_ARB_E_MASK 0x7173#define MME1_RTR_HBW_WR_RQ_W_ARB_S_SHIFT 8174#define MME1_RTR_HBW_WR_RQ_W_ARB_S_MASK 0x700175#define MME1_RTR_HBW_WR_RQ_W_ARB_N_SHIFT 16176#define MME1_RTR_HBW_WR_RQ_W_ARB_N_MASK 0x70000177#define MME1_RTR_HBW_WR_RQ_W_ARB_L_SHIFT 24178#define MME1_RTR_HBW_WR_RQ_W_ARB_L_MASK 0x7000000179 180/* MME1_RTR_HBW_WR_RQ_N_ARB */181#define MME1_RTR_HBW_WR_RQ_N_ARB_W_SHIFT 0182#define MME1_RTR_HBW_WR_RQ_N_ARB_W_MASK 0x7183#define MME1_RTR_HBW_WR_RQ_N_ARB_E_SHIFT 8184#define MME1_RTR_HBW_WR_RQ_N_ARB_E_MASK 0x700185#define MME1_RTR_HBW_WR_RQ_N_ARB_S_SHIFT 16186#define MME1_RTR_HBW_WR_RQ_N_ARB_S_MASK 0x70000187#define MME1_RTR_HBW_WR_RQ_N_ARB_L_SHIFT 24188#define MME1_RTR_HBW_WR_RQ_N_ARB_L_MASK 0x7000000189 190/* MME1_RTR_HBW_WR_RQ_S_ARB */191#define MME1_RTR_HBW_WR_RQ_S_ARB_W_SHIFT 0192#define MME1_RTR_HBW_WR_RQ_S_ARB_W_MASK 0x7193#define MME1_RTR_HBW_WR_RQ_S_ARB_E_SHIFT 8194#define MME1_RTR_HBW_WR_RQ_S_ARB_E_MASK 0x700195#define MME1_RTR_HBW_WR_RQ_S_ARB_N_SHIFT 16196#define MME1_RTR_HBW_WR_RQ_S_ARB_N_MASK 0x70000197#define MME1_RTR_HBW_WR_RQ_S_ARB_L_SHIFT 24198#define MME1_RTR_HBW_WR_RQ_S_ARB_L_MASK 0x7000000199 200/* MME1_RTR_HBW_WR_RQ_L_ARB */201#define MME1_RTR_HBW_WR_RQ_L_ARB_W_SHIFT 0202#define MME1_RTR_HBW_WR_RQ_L_ARB_W_MASK 0x7203#define MME1_RTR_HBW_WR_RQ_L_ARB_E_SHIFT 8204#define MME1_RTR_HBW_WR_RQ_L_ARB_E_MASK 0x700205#define MME1_RTR_HBW_WR_RQ_L_ARB_S_SHIFT 16206#define MME1_RTR_HBW_WR_RQ_L_ARB_S_MASK 0x70000207#define MME1_RTR_HBW_WR_RQ_L_ARB_N_SHIFT 24208#define MME1_RTR_HBW_WR_RQ_L_ARB_N_MASK 0x7000000209 210/* MME1_RTR_HBW_WR_RS_E_ARB */211#define MME1_RTR_HBW_WR_RS_E_ARB_W_SHIFT 0212#define MME1_RTR_HBW_WR_RS_E_ARB_W_MASK 0x7213#define MME1_RTR_HBW_WR_RS_E_ARB_S_SHIFT 8214#define MME1_RTR_HBW_WR_RS_E_ARB_S_MASK 0x700215#define MME1_RTR_HBW_WR_RS_E_ARB_N_SHIFT 16216#define MME1_RTR_HBW_WR_RS_E_ARB_N_MASK 0x70000217#define MME1_RTR_HBW_WR_RS_E_ARB_L_SHIFT 24218#define MME1_RTR_HBW_WR_RS_E_ARB_L_MASK 0x7000000219 220/* MME1_RTR_HBW_WR_RS_W_ARB */221#define MME1_RTR_HBW_WR_RS_W_ARB_E_SHIFT 0222#define MME1_RTR_HBW_WR_RS_W_ARB_E_MASK 0x7223#define MME1_RTR_HBW_WR_RS_W_ARB_S_SHIFT 8224#define MME1_RTR_HBW_WR_RS_W_ARB_S_MASK 0x700225#define MME1_RTR_HBW_WR_RS_W_ARB_N_SHIFT 16226#define MME1_RTR_HBW_WR_RS_W_ARB_N_MASK 0x70000227#define MME1_RTR_HBW_WR_RS_W_ARB_L_SHIFT 24228#define MME1_RTR_HBW_WR_RS_W_ARB_L_MASK 0x7000000229 230/* MME1_RTR_HBW_WR_RS_N_ARB */231#define MME1_RTR_HBW_WR_RS_N_ARB_W_SHIFT 0232#define MME1_RTR_HBW_WR_RS_N_ARB_W_MASK 0x7233#define MME1_RTR_HBW_WR_RS_N_ARB_E_SHIFT 8234#define MME1_RTR_HBW_WR_RS_N_ARB_E_MASK 0x700235#define MME1_RTR_HBW_WR_RS_N_ARB_S_SHIFT 16236#define MME1_RTR_HBW_WR_RS_N_ARB_S_MASK 0x70000237#define MME1_RTR_HBW_WR_RS_N_ARB_L_SHIFT 24238#define MME1_RTR_HBW_WR_RS_N_ARB_L_MASK 0x7000000239 240/* MME1_RTR_HBW_WR_RS_S_ARB */241#define MME1_RTR_HBW_WR_RS_S_ARB_W_SHIFT 0242#define MME1_RTR_HBW_WR_RS_S_ARB_W_MASK 0x7243#define MME1_RTR_HBW_WR_RS_S_ARB_E_SHIFT 8244#define MME1_RTR_HBW_WR_RS_S_ARB_E_MASK 0x700245#define MME1_RTR_HBW_WR_RS_S_ARB_N_SHIFT 16246#define MME1_RTR_HBW_WR_RS_S_ARB_N_MASK 0x70000247#define MME1_RTR_HBW_WR_RS_S_ARB_L_SHIFT 24248#define MME1_RTR_HBW_WR_RS_S_ARB_L_MASK 0x7000000249 250/* MME1_RTR_HBW_WR_RS_L_ARB */251#define MME1_RTR_HBW_WR_RS_L_ARB_W_SHIFT 0252#define MME1_RTR_HBW_WR_RS_L_ARB_W_MASK 0x7253#define MME1_RTR_HBW_WR_RS_L_ARB_E_SHIFT 8254#define MME1_RTR_HBW_WR_RS_L_ARB_E_MASK 0x700255#define MME1_RTR_HBW_WR_RS_L_ARB_S_SHIFT 16256#define MME1_RTR_HBW_WR_RS_L_ARB_S_MASK 0x70000257#define MME1_RTR_HBW_WR_RS_L_ARB_N_SHIFT 24258#define MME1_RTR_HBW_WR_RS_L_ARB_N_MASK 0x7000000259 260/* MME1_RTR_LBW_RD_RQ_E_ARB */261#define MME1_RTR_LBW_RD_RQ_E_ARB_W_SHIFT 0262#define MME1_RTR_LBW_RD_RQ_E_ARB_W_MASK 0x7263#define MME1_RTR_LBW_RD_RQ_E_ARB_S_SHIFT 8264#define MME1_RTR_LBW_RD_RQ_E_ARB_S_MASK 0x700265#define MME1_RTR_LBW_RD_RQ_E_ARB_N_SHIFT 16266#define MME1_RTR_LBW_RD_RQ_E_ARB_N_MASK 0x70000267#define MME1_RTR_LBW_RD_RQ_E_ARB_L_SHIFT 24268#define MME1_RTR_LBW_RD_RQ_E_ARB_L_MASK 0x7000000269 270/* MME1_RTR_LBW_RD_RQ_W_ARB */271#define MME1_RTR_LBW_RD_RQ_W_ARB_E_SHIFT 0272#define MME1_RTR_LBW_RD_RQ_W_ARB_E_MASK 0x7273#define MME1_RTR_LBW_RD_RQ_W_ARB_S_SHIFT 8274#define MME1_RTR_LBW_RD_RQ_W_ARB_S_MASK 0x700275#define MME1_RTR_LBW_RD_RQ_W_ARB_N_SHIFT 16276#define MME1_RTR_LBW_RD_RQ_W_ARB_N_MASK 0x70000277#define MME1_RTR_LBW_RD_RQ_W_ARB_L_SHIFT 24278#define MME1_RTR_LBW_RD_RQ_W_ARB_L_MASK 0x7000000279 280/* MME1_RTR_LBW_RD_RQ_N_ARB */281#define MME1_RTR_LBW_RD_RQ_N_ARB_W_SHIFT 0282#define MME1_RTR_LBW_RD_RQ_N_ARB_W_MASK 0x7283#define MME1_RTR_LBW_RD_RQ_N_ARB_E_SHIFT 8284#define MME1_RTR_LBW_RD_RQ_N_ARB_E_MASK 0x700285#define MME1_RTR_LBW_RD_RQ_N_ARB_S_SHIFT 16286#define MME1_RTR_LBW_RD_RQ_N_ARB_S_MASK 0x70000287#define MME1_RTR_LBW_RD_RQ_N_ARB_L_SHIFT 24288#define MME1_RTR_LBW_RD_RQ_N_ARB_L_MASK 0x7000000289 290/* MME1_RTR_LBW_RD_RQ_S_ARB */291#define MME1_RTR_LBW_RD_RQ_S_ARB_W_SHIFT 0292#define MME1_RTR_LBW_RD_RQ_S_ARB_W_MASK 0x7293#define MME1_RTR_LBW_RD_RQ_S_ARB_E_SHIFT 8294#define MME1_RTR_LBW_RD_RQ_S_ARB_E_MASK 0x700295#define MME1_RTR_LBW_RD_RQ_S_ARB_N_SHIFT 16296#define MME1_RTR_LBW_RD_RQ_S_ARB_N_MASK 0x70000297#define MME1_RTR_LBW_RD_RQ_S_ARB_L_SHIFT 24298#define MME1_RTR_LBW_RD_RQ_S_ARB_L_MASK 0x7000000299 300/* MME1_RTR_LBW_RD_RQ_L_ARB */301#define MME1_RTR_LBW_RD_RQ_L_ARB_W_SHIFT 0302#define MME1_RTR_LBW_RD_RQ_L_ARB_W_MASK 0x7303#define MME1_RTR_LBW_RD_RQ_L_ARB_E_SHIFT 8304#define MME1_RTR_LBW_RD_RQ_L_ARB_E_MASK 0x700305#define MME1_RTR_LBW_RD_RQ_L_ARB_S_SHIFT 16306#define MME1_RTR_LBW_RD_RQ_L_ARB_S_MASK 0x70000307#define MME1_RTR_LBW_RD_RQ_L_ARB_N_SHIFT 24308#define MME1_RTR_LBW_RD_RQ_L_ARB_N_MASK 0x7000000309 310/* MME1_RTR_LBW_E_ARB_MAX */311#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_SHIFT 0312#define MME1_RTR_LBW_E_ARB_MAX_CREDIT_MASK 0x3F313 314/* MME1_RTR_LBW_W_ARB_MAX */315#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_SHIFT 0316#define MME1_RTR_LBW_W_ARB_MAX_CREDIT_MASK 0x3F317 318/* MME1_RTR_LBW_N_ARB_MAX */319#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_SHIFT 0320#define MME1_RTR_LBW_N_ARB_MAX_CREDIT_MASK 0x3F321 322/* MME1_RTR_LBW_S_ARB_MAX */323#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_SHIFT 0324#define MME1_RTR_LBW_S_ARB_MAX_CREDIT_MASK 0x3F325 326/* MME1_RTR_LBW_L_ARB_MAX */327#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_SHIFT 0328#define MME1_RTR_LBW_L_ARB_MAX_CREDIT_MASK 0x3F329 330/* MME1_RTR_LBW_SRAM_MAX_CREDIT */331#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_SHIFT 0332#define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_MASK 0x3F333#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_SHIFT 8334#define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_MASK 0x3F00335 336/* MME1_RTR_LBW_RD_RS_E_ARB */337#define MME1_RTR_LBW_RD_RS_E_ARB_W_SHIFT 0338#define MME1_RTR_LBW_RD_RS_E_ARB_W_MASK 0x7339#define MME1_RTR_LBW_RD_RS_E_ARB_S_SHIFT 8340#define MME1_RTR_LBW_RD_RS_E_ARB_S_MASK 0x700341#define MME1_RTR_LBW_RD_RS_E_ARB_N_SHIFT 16342#define MME1_RTR_LBW_RD_RS_E_ARB_N_MASK 0x70000343#define MME1_RTR_LBW_RD_RS_E_ARB_L_SHIFT 24344#define MME1_RTR_LBW_RD_RS_E_ARB_L_MASK 0x7000000345 346/* MME1_RTR_LBW_RD_RS_W_ARB */347#define MME1_RTR_LBW_RD_RS_W_ARB_E_SHIFT 0348#define MME1_RTR_LBW_RD_RS_W_ARB_E_MASK 0x7349#define MME1_RTR_LBW_RD_RS_W_ARB_S_SHIFT 8350#define MME1_RTR_LBW_RD_RS_W_ARB_S_MASK 0x700351#define MME1_RTR_LBW_RD_RS_W_ARB_N_SHIFT 16352#define MME1_RTR_LBW_RD_RS_W_ARB_N_MASK 0x70000353#define MME1_RTR_LBW_RD_RS_W_ARB_L_SHIFT 24354#define MME1_RTR_LBW_RD_RS_W_ARB_L_MASK 0x7000000355 356/* MME1_RTR_LBW_RD_RS_N_ARB */357#define MME1_RTR_LBW_RD_RS_N_ARB_W_SHIFT 0358#define MME1_RTR_LBW_RD_RS_N_ARB_W_MASK 0x7359#define MME1_RTR_LBW_RD_RS_N_ARB_E_SHIFT 8360#define MME1_RTR_LBW_RD_RS_N_ARB_E_MASK 0x700361#define MME1_RTR_LBW_RD_RS_N_ARB_S_SHIFT 16362#define MME1_RTR_LBW_RD_RS_N_ARB_S_MASK 0x70000363#define MME1_RTR_LBW_RD_RS_N_ARB_L_SHIFT 24364#define MME1_RTR_LBW_RD_RS_N_ARB_L_MASK 0x7000000365 366/* MME1_RTR_LBW_RD_RS_S_ARB */367#define MME1_RTR_LBW_RD_RS_S_ARB_W_SHIFT 0368#define MME1_RTR_LBW_RD_RS_S_ARB_W_MASK 0x7369#define MME1_RTR_LBW_RD_RS_S_ARB_E_SHIFT 8370#define MME1_RTR_LBW_RD_RS_S_ARB_E_MASK 0x700371#define MME1_RTR_LBW_RD_RS_S_ARB_N_SHIFT 16372#define MME1_RTR_LBW_RD_RS_S_ARB_N_MASK 0x70000373#define MME1_RTR_LBW_RD_RS_S_ARB_L_SHIFT 24374#define MME1_RTR_LBW_RD_RS_S_ARB_L_MASK 0x7000000375 376/* MME1_RTR_LBW_RD_RS_L_ARB */377#define MME1_RTR_LBW_RD_RS_L_ARB_W_SHIFT 0378#define MME1_RTR_LBW_RD_RS_L_ARB_W_MASK 0x7379#define MME1_RTR_LBW_RD_RS_L_ARB_E_SHIFT 8380#define MME1_RTR_LBW_RD_RS_L_ARB_E_MASK 0x700381#define MME1_RTR_LBW_RD_RS_L_ARB_S_SHIFT 16382#define MME1_RTR_LBW_RD_RS_L_ARB_S_MASK 0x70000383#define MME1_RTR_LBW_RD_RS_L_ARB_N_SHIFT 24384#define MME1_RTR_LBW_RD_RS_L_ARB_N_MASK 0x7000000385 386/* MME1_RTR_LBW_WR_RQ_E_ARB */387#define MME1_RTR_LBW_WR_RQ_E_ARB_W_SHIFT 0388#define MME1_RTR_LBW_WR_RQ_E_ARB_W_MASK 0x7389#define MME1_RTR_LBW_WR_RQ_E_ARB_S_SHIFT 8390#define MME1_RTR_LBW_WR_RQ_E_ARB_S_MASK 0x700391#define MME1_RTR_LBW_WR_RQ_E_ARB_N_SHIFT 16392#define MME1_RTR_LBW_WR_RQ_E_ARB_N_MASK 0x70000393#define MME1_RTR_LBW_WR_RQ_E_ARB_L_SHIFT 24394#define MME1_RTR_LBW_WR_RQ_E_ARB_L_MASK 0x7000000395 396/* MME1_RTR_LBW_WR_RQ_W_ARB */397#define MME1_RTR_LBW_WR_RQ_W_ARB_E_SHIFT 0398#define MME1_RTR_LBW_WR_RQ_W_ARB_E_MASK 0x7399#define MME1_RTR_LBW_WR_RQ_W_ARB_S_SHIFT 8400#define MME1_RTR_LBW_WR_RQ_W_ARB_S_MASK 0x700401#define MME1_RTR_LBW_WR_RQ_W_ARB_N_SHIFT 16402#define MME1_RTR_LBW_WR_RQ_W_ARB_N_MASK 0x70000403#define MME1_RTR_LBW_WR_RQ_W_ARB_L_SHIFT 24404#define MME1_RTR_LBW_WR_RQ_W_ARB_L_MASK 0x7000000405 406/* MME1_RTR_LBW_WR_RQ_N_ARB */407#define MME1_RTR_LBW_WR_RQ_N_ARB_W_SHIFT 0408#define MME1_RTR_LBW_WR_RQ_N_ARB_W_MASK 0x7409#define MME1_RTR_LBW_WR_RQ_N_ARB_E_SHIFT 8410#define MME1_RTR_LBW_WR_RQ_N_ARB_E_MASK 0x700411#define MME1_RTR_LBW_WR_RQ_N_ARB_S_SHIFT 16412#define MME1_RTR_LBW_WR_RQ_N_ARB_S_MASK 0x70000413#define MME1_RTR_LBW_WR_RQ_N_ARB_L_SHIFT 24414#define MME1_RTR_LBW_WR_RQ_N_ARB_L_MASK 0x7000000415 416/* MME1_RTR_LBW_WR_RQ_S_ARB */417#define MME1_RTR_LBW_WR_RQ_S_ARB_W_SHIFT 0418#define MME1_RTR_LBW_WR_RQ_S_ARB_W_MASK 0x7419#define MME1_RTR_LBW_WR_RQ_S_ARB_E_SHIFT 8420#define MME1_RTR_LBW_WR_RQ_S_ARB_E_MASK 0x700421#define MME1_RTR_LBW_WR_RQ_S_ARB_N_SHIFT 16422#define MME1_RTR_LBW_WR_RQ_S_ARB_N_MASK 0x70000423#define MME1_RTR_LBW_WR_RQ_S_ARB_L_SHIFT 24424#define MME1_RTR_LBW_WR_RQ_S_ARB_L_MASK 0x7000000425 426/* MME1_RTR_LBW_WR_RQ_L_ARB */427#define MME1_RTR_LBW_WR_RQ_L_ARB_W_SHIFT 0428#define MME1_RTR_LBW_WR_RQ_L_ARB_W_MASK 0x7429#define MME1_RTR_LBW_WR_RQ_L_ARB_E_SHIFT 8430#define MME1_RTR_LBW_WR_RQ_L_ARB_E_MASK 0x700431#define MME1_RTR_LBW_WR_RQ_L_ARB_S_SHIFT 16432#define MME1_RTR_LBW_WR_RQ_L_ARB_S_MASK 0x70000433#define MME1_RTR_LBW_WR_RQ_L_ARB_N_SHIFT 24434#define MME1_RTR_LBW_WR_RQ_L_ARB_N_MASK 0x7000000435 436/* MME1_RTR_LBW_WR_RS_E_ARB */437#define MME1_RTR_LBW_WR_RS_E_ARB_W_SHIFT 0438#define MME1_RTR_LBW_WR_RS_E_ARB_W_MASK 0x7439#define MME1_RTR_LBW_WR_RS_E_ARB_S_SHIFT 8440#define MME1_RTR_LBW_WR_RS_E_ARB_S_MASK 0x700441#define MME1_RTR_LBW_WR_RS_E_ARB_N_SHIFT 16442#define MME1_RTR_LBW_WR_RS_E_ARB_N_MASK 0x70000443#define MME1_RTR_LBW_WR_RS_E_ARB_L_SHIFT 24444#define MME1_RTR_LBW_WR_RS_E_ARB_L_MASK 0x7000000445 446/* MME1_RTR_LBW_WR_RS_W_ARB */447#define MME1_RTR_LBW_WR_RS_W_ARB_E_SHIFT 0448#define MME1_RTR_LBW_WR_RS_W_ARB_E_MASK 0x7449#define MME1_RTR_LBW_WR_RS_W_ARB_S_SHIFT 8450#define MME1_RTR_LBW_WR_RS_W_ARB_S_MASK 0x700451#define MME1_RTR_LBW_WR_RS_W_ARB_N_SHIFT 16452#define MME1_RTR_LBW_WR_RS_W_ARB_N_MASK 0x70000453#define MME1_RTR_LBW_WR_RS_W_ARB_L_SHIFT 24454#define MME1_RTR_LBW_WR_RS_W_ARB_L_MASK 0x7000000455 456/* MME1_RTR_LBW_WR_RS_N_ARB */457#define MME1_RTR_LBW_WR_RS_N_ARB_W_SHIFT 0458#define MME1_RTR_LBW_WR_RS_N_ARB_W_MASK 0x7459#define MME1_RTR_LBW_WR_RS_N_ARB_E_SHIFT 8460#define MME1_RTR_LBW_WR_RS_N_ARB_E_MASK 0x700461#define MME1_RTR_LBW_WR_RS_N_ARB_S_SHIFT 16462#define MME1_RTR_LBW_WR_RS_N_ARB_S_MASK 0x70000463#define MME1_RTR_LBW_WR_RS_N_ARB_L_SHIFT 24464#define MME1_RTR_LBW_WR_RS_N_ARB_L_MASK 0x7000000465 466/* MME1_RTR_LBW_WR_RS_S_ARB */467#define MME1_RTR_LBW_WR_RS_S_ARB_W_SHIFT 0468#define MME1_RTR_LBW_WR_RS_S_ARB_W_MASK 0x7469#define MME1_RTR_LBW_WR_RS_S_ARB_E_SHIFT 8470#define MME1_RTR_LBW_WR_RS_S_ARB_E_MASK 0x700471#define MME1_RTR_LBW_WR_RS_S_ARB_N_SHIFT 16472#define MME1_RTR_LBW_WR_RS_S_ARB_N_MASK 0x70000473#define MME1_RTR_LBW_WR_RS_S_ARB_L_SHIFT 24474#define MME1_RTR_LBW_WR_RS_S_ARB_L_MASK 0x7000000475 476/* MME1_RTR_LBW_WR_RS_L_ARB */477#define MME1_RTR_LBW_WR_RS_L_ARB_W_SHIFT 0478#define MME1_RTR_LBW_WR_RS_L_ARB_W_MASK 0x7479#define MME1_RTR_LBW_WR_RS_L_ARB_E_SHIFT 8480#define MME1_RTR_LBW_WR_RS_L_ARB_E_MASK 0x700481#define MME1_RTR_LBW_WR_RS_L_ARB_S_SHIFT 16482#define MME1_RTR_LBW_WR_RS_L_ARB_S_MASK 0x70000483#define MME1_RTR_LBW_WR_RS_L_ARB_N_SHIFT 24484#define MME1_RTR_LBW_WR_RS_L_ARB_N_MASK 0x7000000485 486/* MME1_RTR_DBG_E_ARB */487#define MME1_RTR_DBG_E_ARB_W_SHIFT 0488#define MME1_RTR_DBG_E_ARB_W_MASK 0x7489#define MME1_RTR_DBG_E_ARB_S_SHIFT 8490#define MME1_RTR_DBG_E_ARB_S_MASK 0x700491#define MME1_RTR_DBG_E_ARB_N_SHIFT 16492#define MME1_RTR_DBG_E_ARB_N_MASK 0x70000493#define MME1_RTR_DBG_E_ARB_L_SHIFT 24494#define MME1_RTR_DBG_E_ARB_L_MASK 0x7000000495 496/* MME1_RTR_DBG_W_ARB */497#define MME1_RTR_DBG_W_ARB_E_SHIFT 0498#define MME1_RTR_DBG_W_ARB_E_MASK 0x7499#define MME1_RTR_DBG_W_ARB_S_SHIFT 8500#define MME1_RTR_DBG_W_ARB_S_MASK 0x700501#define MME1_RTR_DBG_W_ARB_N_SHIFT 16502#define MME1_RTR_DBG_W_ARB_N_MASK 0x70000503#define MME1_RTR_DBG_W_ARB_L_SHIFT 24504#define MME1_RTR_DBG_W_ARB_L_MASK 0x7000000505 506/* MME1_RTR_DBG_N_ARB */507#define MME1_RTR_DBG_N_ARB_W_SHIFT 0508#define MME1_RTR_DBG_N_ARB_W_MASK 0x7509#define MME1_RTR_DBG_N_ARB_E_SHIFT 8510#define MME1_RTR_DBG_N_ARB_E_MASK 0x700511#define MME1_RTR_DBG_N_ARB_S_SHIFT 16512#define MME1_RTR_DBG_N_ARB_S_MASK 0x70000513#define MME1_RTR_DBG_N_ARB_L_SHIFT 24514#define MME1_RTR_DBG_N_ARB_L_MASK 0x7000000515 516/* MME1_RTR_DBG_S_ARB */517#define MME1_RTR_DBG_S_ARB_W_SHIFT 0518#define MME1_RTR_DBG_S_ARB_W_MASK 0x7519#define MME1_RTR_DBG_S_ARB_E_SHIFT 8520#define MME1_RTR_DBG_S_ARB_E_MASK 0x700521#define MME1_RTR_DBG_S_ARB_N_SHIFT 16522#define MME1_RTR_DBG_S_ARB_N_MASK 0x70000523#define MME1_RTR_DBG_S_ARB_L_SHIFT 24524#define MME1_RTR_DBG_S_ARB_L_MASK 0x7000000525 526/* MME1_RTR_DBG_L_ARB */527#define MME1_RTR_DBG_L_ARB_W_SHIFT 0528#define MME1_RTR_DBG_L_ARB_W_MASK 0x7529#define MME1_RTR_DBG_L_ARB_E_SHIFT 8530#define MME1_RTR_DBG_L_ARB_E_MASK 0x700531#define MME1_RTR_DBG_L_ARB_S_SHIFT 16532#define MME1_RTR_DBG_L_ARB_S_MASK 0x70000533#define MME1_RTR_DBG_L_ARB_N_SHIFT 24534#define MME1_RTR_DBG_L_ARB_N_MASK 0x7000000535 536/* MME1_RTR_DBG_E_ARB_MAX */537#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0538#define MME1_RTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F539 540/* MME1_RTR_DBG_W_ARB_MAX */541#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0542#define MME1_RTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F543 544/* MME1_RTR_DBG_N_ARB_MAX */545#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0546#define MME1_RTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F547 548/* MME1_RTR_DBG_S_ARB_MAX */549#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0550#define MME1_RTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F551 552/* MME1_RTR_DBG_L_ARB_MAX */553#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0554#define MME1_RTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F555 556/* MME1_RTR_SPLIT_COEF */557#define MME1_RTR_SPLIT_COEF_VAL_SHIFT 0558#define MME1_RTR_SPLIT_COEF_VAL_MASK 0xFFFF559 560/* MME1_RTR_SPLIT_CFG */561#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0562#define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1563#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1564#define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2565#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2566#define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC567#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 4568#define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x10569#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 5570#define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x20571#define MME1_RTR_SPLIT_CFG_B2B_OPT_SHIFT 6572#define MME1_RTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0573 574/* MME1_RTR_SPLIT_RD_SAT */575#define MME1_RTR_SPLIT_RD_SAT_VAL_SHIFT 0576#define MME1_RTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF577 578/* MME1_RTR_SPLIT_RD_RST_TOKEN */579#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0580#define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF581 582/* MME1_RTR_SPLIT_RD_TIMEOUT */583#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0584#define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF585 586/* MME1_RTR_SPLIT_WR_SAT */587#define MME1_RTR_SPLIT_WR_SAT_VAL_SHIFT 0588#define MME1_RTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF589 590/* MME1_RTR_WPLIT_WR_TST_TOLEN */591#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0592#define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF593 594/* MME1_RTR_SPLIT_WR_TIMEOUT */595#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0596#define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF597 598/* MME1_RTR_HBW_RANGE_HIT */599#define MME1_RTR_HBW_RANGE_HIT_IND_SHIFT 0600#define MME1_RTR_HBW_RANGE_HIT_IND_MASK 0xFF601 602/* MME1_RTR_HBW_RANGE_MASK_L */603#define MME1_RTR_HBW_RANGE_MASK_L_VAL_SHIFT 0604#define MME1_RTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF605 606/* MME1_RTR_HBW_RANGE_MASK_H */607#define MME1_RTR_HBW_RANGE_MASK_H_VAL_SHIFT 0608#define MME1_RTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF609 610/* MME1_RTR_HBW_RANGE_BASE_L */611#define MME1_RTR_HBW_RANGE_BASE_L_VAL_SHIFT 0612#define MME1_RTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF613 614/* MME1_RTR_HBW_RANGE_BASE_H */615#define MME1_RTR_HBW_RANGE_BASE_H_VAL_SHIFT 0616#define MME1_RTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF617 618/* MME1_RTR_LBW_RANGE_HIT */619#define MME1_RTR_LBW_RANGE_HIT_IND_SHIFT 0620#define MME1_RTR_LBW_RANGE_HIT_IND_MASK 0xFFFF621 622/* MME1_RTR_LBW_RANGE_MASK */623#define MME1_RTR_LBW_RANGE_MASK_VAL_SHIFT 0624#define MME1_RTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF625 626/* MME1_RTR_LBW_RANGE_BASE */627#define MME1_RTR_LBW_RANGE_BASE_VAL_SHIFT 0628#define MME1_RTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF629 630/* MME1_RTR_RGLTR */631#define MME1_RTR_RGLTR_WR_EN_SHIFT 0632#define MME1_RTR_RGLTR_WR_EN_MASK 0x1633#define MME1_RTR_RGLTR_RD_EN_SHIFT 4634#define MME1_RTR_RGLTR_RD_EN_MASK 0x10635 636/* MME1_RTR_RGLTR_WR_RESULT */637#define MME1_RTR_RGLTR_WR_RESULT_VAL_SHIFT 0638#define MME1_RTR_RGLTR_WR_RESULT_VAL_MASK 0xFF639 640/* MME1_RTR_RGLTR_RD_RESULT */641#define MME1_RTR_RGLTR_RD_RESULT_VAL_SHIFT 0642#define MME1_RTR_RGLTR_RD_RESULT_VAL_MASK 0xFF643 644/* MME1_RTR_SCRAMB_EN */645#define MME1_RTR_SCRAMB_EN_VAL_SHIFT 0646#define MME1_RTR_SCRAMB_EN_VAL_MASK 0x1647 648/* MME1_RTR_NON_LIN_SCRAMB */649#define MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT 0650#define MME1_RTR_NON_LIN_SCRAMB_EN_MASK 0x1651 652#endif /* ASIC_REG_MME1_RTR_MASKS_H_ */653