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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME1_RTR_REGS_H_14#define ASIC_REG_MME1_RTR_REGS_H_15 16/*17 *****************************************18 * MME1_RTR (Prototype: MME_RTR)19 *****************************************20 */21 22#define mmMME1_RTR_HBW_RD_RQ_E_ARB 0x4010023 24#define mmMME1_RTR_HBW_RD_RQ_W_ARB 0x4010425 26#define mmMME1_RTR_HBW_RD_RQ_N_ARB 0x4010827 28#define mmMME1_RTR_HBW_RD_RQ_S_ARB 0x4010C29 30#define mmMME1_RTR_HBW_RD_RQ_L_ARB 0x4011031 32#define mmMME1_RTR_HBW_E_ARB_MAX 0x4012033 34#define mmMME1_RTR_HBW_W_ARB_MAX 0x4012435 36#define mmMME1_RTR_HBW_N_ARB_MAX 0x4012837 38#define mmMME1_RTR_HBW_S_ARB_MAX 0x4012C39 40#define mmMME1_RTR_HBW_L_ARB_MAX 0x4013041 42#define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT 0x4014043 44#define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT 0x4014445 46#define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT 0x4014847 48#define mmMME1_RTR_HBW_RD_RS_E_ARB 0x4015049 50#define mmMME1_RTR_HBW_RD_RS_W_ARB 0x4015451 52#define mmMME1_RTR_HBW_RD_RS_N_ARB 0x4015853 54#define mmMME1_RTR_HBW_RD_RS_S_ARB 0x4015C55 56#define mmMME1_RTR_HBW_RD_RS_L_ARB 0x4016057 58#define mmMME1_RTR_HBW_WR_RQ_E_ARB 0x4017059 60#define mmMME1_RTR_HBW_WR_RQ_W_ARB 0x4017461 62#define mmMME1_RTR_HBW_WR_RQ_N_ARB 0x4017863 64#define mmMME1_RTR_HBW_WR_RQ_S_ARB 0x4017C65 66#define mmMME1_RTR_HBW_WR_RQ_L_ARB 0x4018067 68#define mmMME1_RTR_HBW_WR_RS_E_ARB 0x4019069 70#define mmMME1_RTR_HBW_WR_RS_W_ARB 0x4019471 72#define mmMME1_RTR_HBW_WR_RS_N_ARB 0x4019873 74#define mmMME1_RTR_HBW_WR_RS_S_ARB 0x4019C75 76#define mmMME1_RTR_HBW_WR_RS_L_ARB 0x401A077 78#define mmMME1_RTR_LBW_RD_RQ_E_ARB 0x4020079 80#define mmMME1_RTR_LBW_RD_RQ_W_ARB 0x4020481 82#define mmMME1_RTR_LBW_RD_RQ_N_ARB 0x4020883 84#define mmMME1_RTR_LBW_RD_RQ_S_ARB 0x4020C85 86#define mmMME1_RTR_LBW_RD_RQ_L_ARB 0x4021087 88#define mmMME1_RTR_LBW_E_ARB_MAX 0x4022089 90#define mmMME1_RTR_LBW_W_ARB_MAX 0x4022491 92#define mmMME1_RTR_LBW_N_ARB_MAX 0x4022893 94#define mmMME1_RTR_LBW_S_ARB_MAX 0x4022C95 96#define mmMME1_RTR_LBW_L_ARB_MAX 0x4023097 98#define mmMME1_RTR_LBW_SRAM_MAX_CREDIT 0x4024099 100#define mmMME1_RTR_LBW_RD_RS_E_ARB 0x40250101 102#define mmMME1_RTR_LBW_RD_RS_W_ARB 0x40254103 104#define mmMME1_RTR_LBW_RD_RS_N_ARB 0x40258105 106#define mmMME1_RTR_LBW_RD_RS_S_ARB 0x4025C107 108#define mmMME1_RTR_LBW_RD_RS_L_ARB 0x40260109 110#define mmMME1_RTR_LBW_WR_RQ_E_ARB 0x40270111 112#define mmMME1_RTR_LBW_WR_RQ_W_ARB 0x40274113 114#define mmMME1_RTR_LBW_WR_RQ_N_ARB 0x40278115 116#define mmMME1_RTR_LBW_WR_RQ_S_ARB 0x4027C117 118#define mmMME1_RTR_LBW_WR_RQ_L_ARB 0x40280119 120#define mmMME1_RTR_LBW_WR_RS_E_ARB 0x40290121 122#define mmMME1_RTR_LBW_WR_RS_W_ARB 0x40294123 124#define mmMME1_RTR_LBW_WR_RS_N_ARB 0x40298125 126#define mmMME1_RTR_LBW_WR_RS_S_ARB 0x4029C127 128#define mmMME1_RTR_LBW_WR_RS_L_ARB 0x402A0129 130#define mmMME1_RTR_DBG_E_ARB 0x40300131 132#define mmMME1_RTR_DBG_W_ARB 0x40304133 134#define mmMME1_RTR_DBG_N_ARB 0x40308135 136#define mmMME1_RTR_DBG_S_ARB 0x4030C137 138#define mmMME1_RTR_DBG_L_ARB 0x40310139 140#define mmMME1_RTR_DBG_E_ARB_MAX 0x40320141 142#define mmMME1_RTR_DBG_W_ARB_MAX 0x40324143 144#define mmMME1_RTR_DBG_N_ARB_MAX 0x40328145 146#define mmMME1_RTR_DBG_S_ARB_MAX 0x4032C147 148#define mmMME1_RTR_DBG_L_ARB_MAX 0x40330149 150#define mmMME1_RTR_SPLIT_COEF_0 0x40400151 152#define mmMME1_RTR_SPLIT_COEF_1 0x40404153 154#define mmMME1_RTR_SPLIT_COEF_2 0x40408155 156#define mmMME1_RTR_SPLIT_COEF_3 0x4040C157 158#define mmMME1_RTR_SPLIT_COEF_4 0x40410159 160#define mmMME1_RTR_SPLIT_COEF_5 0x40414161 162#define mmMME1_RTR_SPLIT_COEF_6 0x40418163 164#define mmMME1_RTR_SPLIT_COEF_7 0x4041C165 166#define mmMME1_RTR_SPLIT_COEF_8 0x40420167 168#define mmMME1_RTR_SPLIT_COEF_9 0x40424169 170#define mmMME1_RTR_SPLIT_CFG 0x40440171 172#define mmMME1_RTR_SPLIT_RD_SAT 0x40444173 174#define mmMME1_RTR_SPLIT_RD_RST_TOKEN 0x40448175 176#define mmMME1_RTR_SPLIT_RD_TIMEOUT_0 0x4044C177 178#define mmMME1_RTR_SPLIT_RD_TIMEOUT_1 0x40450179 180#define mmMME1_RTR_SPLIT_WR_SAT 0x40454181 182#define mmMME1_RTR_WPLIT_WR_TST_TOLEN 0x40458183 184#define mmMME1_RTR_SPLIT_WR_TIMEOUT_0 0x4045C185 186#define mmMME1_RTR_SPLIT_WR_TIMEOUT_1 0x40460187 188#define mmMME1_RTR_HBW_RANGE_HIT 0x40470189 190#define mmMME1_RTR_HBW_RANGE_MASK_L_0 0x40480191 192#define mmMME1_RTR_HBW_RANGE_MASK_L_1 0x40484193 194#define mmMME1_RTR_HBW_RANGE_MASK_L_2 0x40488195 196#define mmMME1_RTR_HBW_RANGE_MASK_L_3 0x4048C197 198#define mmMME1_RTR_HBW_RANGE_MASK_L_4 0x40490199 200#define mmMME1_RTR_HBW_RANGE_MASK_L_5 0x40494201 202#define mmMME1_RTR_HBW_RANGE_MASK_L_6 0x40498203 204#define mmMME1_RTR_HBW_RANGE_MASK_L_7 0x4049C205 206#define mmMME1_RTR_HBW_RANGE_MASK_H_0 0x404A0207 208#define mmMME1_RTR_HBW_RANGE_MASK_H_1 0x404A4209 210#define mmMME1_RTR_HBW_RANGE_MASK_H_2 0x404A8211 212#define mmMME1_RTR_HBW_RANGE_MASK_H_3 0x404AC213 214#define mmMME1_RTR_HBW_RANGE_MASK_H_4 0x404B0215 216#define mmMME1_RTR_HBW_RANGE_MASK_H_5 0x404B4217 218#define mmMME1_RTR_HBW_RANGE_MASK_H_6 0x404B8219 220#define mmMME1_RTR_HBW_RANGE_MASK_H_7 0x404BC221 222#define mmMME1_RTR_HBW_RANGE_BASE_L_0 0x404C0223 224#define mmMME1_RTR_HBW_RANGE_BASE_L_1 0x404C4225 226#define mmMME1_RTR_HBW_RANGE_BASE_L_2 0x404C8227 228#define mmMME1_RTR_HBW_RANGE_BASE_L_3 0x404CC229 230#define mmMME1_RTR_HBW_RANGE_BASE_L_4 0x404D0231 232#define mmMME1_RTR_HBW_RANGE_BASE_L_5 0x404D4233 234#define mmMME1_RTR_HBW_RANGE_BASE_L_6 0x404D8235 236#define mmMME1_RTR_HBW_RANGE_BASE_L_7 0x404DC237 238#define mmMME1_RTR_HBW_RANGE_BASE_H_0 0x404E0239 240#define mmMME1_RTR_HBW_RANGE_BASE_H_1 0x404E4241 242#define mmMME1_RTR_HBW_RANGE_BASE_H_2 0x404E8243 244#define mmMME1_RTR_HBW_RANGE_BASE_H_3 0x404EC245 246#define mmMME1_RTR_HBW_RANGE_BASE_H_4 0x404F0247 248#define mmMME1_RTR_HBW_RANGE_BASE_H_5 0x404F4249 250#define mmMME1_RTR_HBW_RANGE_BASE_H_6 0x404F8251 252#define mmMME1_RTR_HBW_RANGE_BASE_H_7 0x404FC253 254#define mmMME1_RTR_LBW_RANGE_HIT 0x40500255 256#define mmMME1_RTR_LBW_RANGE_MASK_0 0x40510257 258#define mmMME1_RTR_LBW_RANGE_MASK_1 0x40514259 260#define mmMME1_RTR_LBW_RANGE_MASK_2 0x40518261 262#define mmMME1_RTR_LBW_RANGE_MASK_3 0x4051C263 264#define mmMME1_RTR_LBW_RANGE_MASK_4 0x40520265 266#define mmMME1_RTR_LBW_RANGE_MASK_5 0x40524267 268#define mmMME1_RTR_LBW_RANGE_MASK_6 0x40528269 270#define mmMME1_RTR_LBW_RANGE_MASK_7 0x4052C271 272#define mmMME1_RTR_LBW_RANGE_MASK_8 0x40530273 274#define mmMME1_RTR_LBW_RANGE_MASK_9 0x40534275 276#define mmMME1_RTR_LBW_RANGE_MASK_10 0x40538277 278#define mmMME1_RTR_LBW_RANGE_MASK_11 0x4053C279 280#define mmMME1_RTR_LBW_RANGE_MASK_12 0x40540281 282#define mmMME1_RTR_LBW_RANGE_MASK_13 0x40544283 284#define mmMME1_RTR_LBW_RANGE_MASK_14 0x40548285 286#define mmMME1_RTR_LBW_RANGE_MASK_15 0x4054C287 288#define mmMME1_RTR_LBW_RANGE_BASE_0 0x40550289 290#define mmMME1_RTR_LBW_RANGE_BASE_1 0x40554291 292#define mmMME1_RTR_LBW_RANGE_BASE_2 0x40558293 294#define mmMME1_RTR_LBW_RANGE_BASE_3 0x4055C295 296#define mmMME1_RTR_LBW_RANGE_BASE_4 0x40560297 298#define mmMME1_RTR_LBW_RANGE_BASE_5 0x40564299 300#define mmMME1_RTR_LBW_RANGE_BASE_6 0x40568301 302#define mmMME1_RTR_LBW_RANGE_BASE_7 0x4056C303 304#define mmMME1_RTR_LBW_RANGE_BASE_8 0x40570305 306#define mmMME1_RTR_LBW_RANGE_BASE_9 0x40574307 308#define mmMME1_RTR_LBW_RANGE_BASE_10 0x40578309 310#define mmMME1_RTR_LBW_RANGE_BASE_11 0x4057C311 312#define mmMME1_RTR_LBW_RANGE_BASE_12 0x40580313 314#define mmMME1_RTR_LBW_RANGE_BASE_13 0x40584315 316#define mmMME1_RTR_LBW_RANGE_BASE_14 0x40588317 318#define mmMME1_RTR_LBW_RANGE_BASE_15 0x4058C319 320#define mmMME1_RTR_RGLTR 0x40590321 322#define mmMME1_RTR_RGLTR_WR_RESULT 0x40594323 324#define mmMME1_RTR_RGLTR_RD_RESULT 0x40598325 326#define mmMME1_RTR_SCRAMB_EN 0x40600327 328#define mmMME1_RTR_NON_LIN_SCRAMB 0x40604329 330#endif /* ASIC_REG_MME1_RTR_REGS_H_ */331