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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME_CMDQ_MASKS_H_14#define ASIC_REG_MME_CMDQ_MASKS_H_15 16/*17 *****************************************18 * MME_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22/* MME_CMDQ_GLBL_CFG0 */23#define MME_CMDQ_GLBL_CFG0_PQF_EN_SHIFT 024#define MME_CMDQ_GLBL_CFG0_PQF_EN_MASK 0x125#define MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT 126#define MME_CMDQ_GLBL_CFG0_CQF_EN_MASK 0x227#define MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT 228#define MME_CMDQ_GLBL_CFG0_CP_EN_MASK 0x429#define MME_CMDQ_GLBL_CFG0_DMA_EN_SHIFT 330#define MME_CMDQ_GLBL_CFG0_DMA_EN_MASK 0x831 32/* MME_CMDQ_GLBL_CFG1 */33#define MME_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT 034#define MME_CMDQ_GLBL_CFG1_PQF_STOP_MASK 0x135#define MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT 136#define MME_CMDQ_GLBL_CFG1_CQF_STOP_MASK 0x237#define MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT 238#define MME_CMDQ_GLBL_CFG1_CP_STOP_MASK 0x439#define MME_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT 340#define MME_CMDQ_GLBL_CFG1_DMA_STOP_MASK 0x841#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT 842#define MME_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK 0x10043#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT 944#define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x20045#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT 1046#define MME_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x40047#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT 1148#define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x80049 50/* MME_CMDQ_GLBL_PROT */51#define MME_CMDQ_GLBL_PROT_PQF_PROT_SHIFT 052#define MME_CMDQ_GLBL_PROT_PQF_PROT_MASK 0x153#define MME_CMDQ_GLBL_PROT_CQF_PROT_SHIFT 154#define MME_CMDQ_GLBL_PROT_CQF_PROT_MASK 0x255#define MME_CMDQ_GLBL_PROT_CP_PROT_SHIFT 256#define MME_CMDQ_GLBL_PROT_CP_PROT_MASK 0x457#define MME_CMDQ_GLBL_PROT_DMA_PROT_SHIFT 358#define MME_CMDQ_GLBL_PROT_DMA_PROT_MASK 0x859#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT 460#define MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK 0x1061#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT 562#define MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK 0x2063#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT 664#define MME_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK 0x4065#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT 766#define MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK 0x8067 68/* MME_CMDQ_GLBL_ERR_CFG */69#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 070#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x171#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 172#define MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x273#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 274#define MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x475#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 376#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x877#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 478#define MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1079#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 580#define MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x2081#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 682#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x4083#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 784#define MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x8085#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 886#define MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x10087#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 988#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x20089#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 1090#define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x40091#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 1192#define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x80093 94/* MME_CMDQ_GLBL_ERR_ADDR_LO */95#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT 096#define MME_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF97 98/* MME_CMDQ_GLBL_ERR_ADDR_HI */99#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT 0100#define MME_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF101 102/* MME_CMDQ_GLBL_ERR_WDATA */103#define MME_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT 0104#define MME_CMDQ_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF105 106/* MME_CMDQ_GLBL_SECURE_PROPS */107#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT 0108#define MME_CMDQ_GLBL_SECURE_PROPS_ASID_MASK 0x3FF109#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT 10110#define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400111 112/* MME_CMDQ_GLBL_NON_SECURE_PROPS */113#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0114#define MME_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF115#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10116#define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400117 118/* MME_CMDQ_GLBL_STS0 */119#define MME_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT 0120#define MME_CMDQ_GLBL_STS0_PQF_IDLE_MASK 0x1121#define MME_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT 1122#define MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK 0x2123#define MME_CMDQ_GLBL_STS0_CP_IDLE_SHIFT 2124#define MME_CMDQ_GLBL_STS0_CP_IDLE_MASK 0x4125#define MME_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT 3126#define MME_CMDQ_GLBL_STS0_DMA_IDLE_MASK 0x8127#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT 4128#define MME_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK 0x10129#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT 5130#define MME_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK 0x20131#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT 6132#define MME_CMDQ_GLBL_STS0_CP_IS_STOP_MASK 0x40133#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT 7134#define MME_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK 0x80135 136/* MME_CMDQ_GLBL_STS1 */137#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT 0138#define MME_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK 0x1139#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT 1140#define MME_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK 0x2141#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT 2142#define MME_CMDQ_GLBL_STS1_CP_RD_ERR_MASK 0x4143#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3144#define MME_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8145#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT 4146#define MME_CMDQ_GLBL_STS1_CP_STOP_OP_MASK 0x10147#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5148#define MME_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20149#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT 8150#define MME_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK 0x100151#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT 9152#define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200153#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10154#define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400155#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11156#define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800157 158/* MME_CMDQ_CQ_CFG0 */159#define MME_CMDQ_CQ_CFG0_RESERVED_SHIFT 0160#define MME_CMDQ_CQ_CFG0_RESERVED_MASK 0x1161 162/* MME_CMDQ_CQ_CFG1 */163#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT 0164#define MME_CMDQ_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF165#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT 16166#define MME_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000167 168/* MME_CMDQ_CQ_ARUSER */169#define MME_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT 0170#define MME_CMDQ_CQ_ARUSER_NOSNOOP_MASK 0x1171#define MME_CMDQ_CQ_ARUSER_WORD_SHIFT 1172#define MME_CMDQ_CQ_ARUSER_WORD_MASK 0x2173 174/* MME_CMDQ_CQ_PTR_LO */175#define MME_CMDQ_CQ_PTR_LO_VAL_SHIFT 0176#define MME_CMDQ_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF177 178/* MME_CMDQ_CQ_PTR_HI */179#define MME_CMDQ_CQ_PTR_HI_VAL_SHIFT 0180#define MME_CMDQ_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF181 182/* MME_CMDQ_CQ_TSIZE */183#define MME_CMDQ_CQ_TSIZE_VAL_SHIFT 0184#define MME_CMDQ_CQ_TSIZE_VAL_MASK 0xFFFFFFFF185 186/* MME_CMDQ_CQ_CTL */187#define MME_CMDQ_CQ_CTL_RPT_SHIFT 0188#define MME_CMDQ_CQ_CTL_RPT_MASK 0xFFFF189#define MME_CMDQ_CQ_CTL_CTL_SHIFT 16190#define MME_CMDQ_CQ_CTL_CTL_MASK 0xFFFF0000191 192/* MME_CMDQ_CQ_PTR_LO_STS */193#define MME_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT 0194#define MME_CMDQ_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF195 196/* MME_CMDQ_CQ_PTR_HI_STS */197#define MME_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT 0198#define MME_CMDQ_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF199 200/* MME_CMDQ_CQ_TSIZE_STS */201#define MME_CMDQ_CQ_TSIZE_STS_VAL_SHIFT 0202#define MME_CMDQ_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF203 204/* MME_CMDQ_CQ_CTL_STS */205#define MME_CMDQ_CQ_CTL_STS_RPT_SHIFT 0206#define MME_CMDQ_CQ_CTL_STS_RPT_MASK 0xFFFF207#define MME_CMDQ_CQ_CTL_STS_CTL_SHIFT 16208#define MME_CMDQ_CQ_CTL_STS_CTL_MASK 0xFFFF0000209 210/* MME_CMDQ_CQ_STS0 */211#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0212#define MME_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF213#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT 16214#define MME_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000215 216/* MME_CMDQ_CQ_STS1 */217#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0218#define MME_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF219#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30220#define MME_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000221#define MME_CMDQ_CQ_STS1_CQ_BUSY_SHIFT 31222#define MME_CMDQ_CQ_STS1_CQ_BUSY_MASK 0x80000000223 224/* MME_CMDQ_CQ_RD_RATE_LIM_EN */225#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0226#define MME_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1227 228/* MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN */229#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0230#define MME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF231 232/* MME_CMDQ_CQ_RD_RATE_LIM_SAT */233#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0234#define MME_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF235 236/* MME_CMDQ_CQ_RD_RATE_LIM_TOUT */237#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0238#define MME_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF239 240/* MME_CMDQ_CQ_IFIFO_CNT */241#define MME_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT 0242#define MME_CMDQ_CQ_IFIFO_CNT_VAL_MASK 0x3243 244/* MME_CMDQ_CP_MSG_BASE0_ADDR_LO */245#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0246#define MME_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF247 248/* MME_CMDQ_CP_MSG_BASE0_ADDR_HI */249#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0250#define MME_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF251 252/* MME_CMDQ_CP_MSG_BASE1_ADDR_LO */253#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0254#define MME_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF255 256/* MME_CMDQ_CP_MSG_BASE1_ADDR_HI */257#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0258#define MME_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF259 260/* MME_CMDQ_CP_MSG_BASE2_ADDR_LO */261#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0262#define MME_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF263 264/* MME_CMDQ_CP_MSG_BASE2_ADDR_HI */265#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0266#define MME_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF267 268/* MME_CMDQ_CP_MSG_BASE3_ADDR_LO */269#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0270#define MME_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF271 272/* MME_CMDQ_CP_MSG_BASE3_ADDR_HI */273#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0274#define MME_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF275 276/* MME_CMDQ_CP_LDMA_TSIZE_OFFSET */277#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0278#define MME_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF279 280/* MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET */281#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0282#define MME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF283 284/* MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET */285#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0286#define MME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF287 288/* MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET */289#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0290#define MME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF291 292/* MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET */293#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0294#define MME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF295 296/* MME_CMDQ_CP_LDMA_COMMIT_OFFSET */297#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0298#define MME_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF299 300/* MME_CMDQ_CP_FENCE0_RDATA */301#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT 0302#define MME_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK 0xF303 304/* MME_CMDQ_CP_FENCE1_RDATA */305#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT 0306#define MME_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK 0xF307 308/* MME_CMDQ_CP_FENCE2_RDATA */309#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT 0310#define MME_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK 0xF311 312/* MME_CMDQ_CP_FENCE3_RDATA */313#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT 0314#define MME_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK 0xF315 316/* MME_CMDQ_CP_FENCE0_CNT */317#define MME_CMDQ_CP_FENCE0_CNT_VAL_SHIFT 0318#define MME_CMDQ_CP_FENCE0_CNT_VAL_MASK 0xFF319 320/* MME_CMDQ_CP_FENCE1_CNT */321#define MME_CMDQ_CP_FENCE1_CNT_VAL_SHIFT 0322#define MME_CMDQ_CP_FENCE1_CNT_VAL_MASK 0xFF323 324/* MME_CMDQ_CP_FENCE2_CNT */325#define MME_CMDQ_CP_FENCE2_CNT_VAL_SHIFT 0326#define MME_CMDQ_CP_FENCE2_CNT_VAL_MASK 0xFF327 328/* MME_CMDQ_CP_FENCE3_CNT */329#define MME_CMDQ_CP_FENCE3_CNT_VAL_SHIFT 0330#define MME_CMDQ_CP_FENCE3_CNT_VAL_MASK 0xFF331 332/* MME_CMDQ_CP_STS */333#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0334#define MME_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF335#define MME_CMDQ_CP_STS_ERDY_SHIFT 16336#define MME_CMDQ_CP_STS_ERDY_MASK 0x10000337#define MME_CMDQ_CP_STS_RRDY_SHIFT 17338#define MME_CMDQ_CP_STS_RRDY_MASK 0x20000339#define MME_CMDQ_CP_STS_MRDY_SHIFT 18340#define MME_CMDQ_CP_STS_MRDY_MASK 0x40000341#define MME_CMDQ_CP_STS_SW_STOP_SHIFT 19342#define MME_CMDQ_CP_STS_SW_STOP_MASK 0x80000343#define MME_CMDQ_CP_STS_FENCE_ID_SHIFT 20344#define MME_CMDQ_CP_STS_FENCE_ID_MASK 0x300000345#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT 22346#define MME_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000347 348/* MME_CMDQ_CP_CURRENT_INST_LO */349#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT 0350#define MME_CMDQ_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF351 352/* MME_CMDQ_CP_CURRENT_INST_HI */353#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT 0354#define MME_CMDQ_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF355 356/* MME_CMDQ_CP_BARRIER_CFG */357#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT 0358#define MME_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF359 360/* MME_CMDQ_CP_DBG_0 */361#define MME_CMDQ_CP_DBG_0_VAL_SHIFT 0362#define MME_CMDQ_CP_DBG_0_VAL_MASK 0xFF363 364/* MME_CMDQ_CQ_BUF_ADDR */365#define MME_CMDQ_CQ_BUF_ADDR_VAL_SHIFT 0366#define MME_CMDQ_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF367 368/* MME_CMDQ_CQ_BUF_RDATA */369#define MME_CMDQ_CQ_BUF_RDATA_VAL_SHIFT 0370#define MME_CMDQ_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF371 372#endif /* ASIC_REG_MME_CMDQ_MASKS_H_ */373