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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME_CMDQ_REGS_H_14#define ASIC_REG_MME_CMDQ_REGS_H_15 16/*17 *****************************************18 * MME_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22#define mmMME_CMDQ_GLBL_CFG0 0xD900023 24#define mmMME_CMDQ_GLBL_CFG1 0xD900425 26#define mmMME_CMDQ_GLBL_PROT 0xD900827 28#define mmMME_CMDQ_GLBL_ERR_CFG 0xD900C29 30#define mmMME_CMDQ_GLBL_ERR_ADDR_LO 0xD901031 32#define mmMME_CMDQ_GLBL_ERR_ADDR_HI 0xD901433 34#define mmMME_CMDQ_GLBL_ERR_WDATA 0xD901835 36#define mmMME_CMDQ_GLBL_SECURE_PROPS 0xD901C37 38#define mmMME_CMDQ_GLBL_NON_SECURE_PROPS 0xD902039 40#define mmMME_CMDQ_GLBL_STS0 0xD902441 42#define mmMME_CMDQ_GLBL_STS1 0xD902843 44#define mmMME_CMDQ_CQ_CFG0 0xD90B045 46#define mmMME_CMDQ_CQ_CFG1 0xD90B447 48#define mmMME_CMDQ_CQ_ARUSER 0xD90B849 50#define mmMME_CMDQ_CQ_PTR_LO 0xD90C051 52#define mmMME_CMDQ_CQ_PTR_HI 0xD90C453 54#define mmMME_CMDQ_CQ_TSIZE 0xD90C855 56#define mmMME_CMDQ_CQ_CTL 0xD90CC57 58#define mmMME_CMDQ_CQ_PTR_LO_STS 0xD90D459 60#define mmMME_CMDQ_CQ_PTR_HI_STS 0xD90D861 62#define mmMME_CMDQ_CQ_TSIZE_STS 0xD90DC63 64#define mmMME_CMDQ_CQ_CTL_STS 0xD90E065 66#define mmMME_CMDQ_CQ_STS0 0xD90E467 68#define mmMME_CMDQ_CQ_STS1 0xD90E869 70#define mmMME_CMDQ_CQ_RD_RATE_LIM_EN 0xD90F071 72#define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xD90F473 74#define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT 0xD90F875 76#define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT 0xD90FC77 78#define mmMME_CMDQ_CQ_IFIFO_CNT 0xD910879 80#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO 0xD912081 82#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI 0xD912483 84#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO 0xD912885 86#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI 0xD912C87 88#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO 0xD913089 90#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI 0xD913491 92#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO 0xD913893 94#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI 0xD913C95 96#define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET 0xD914097 98#define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xD914499 100#define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xD9148101 102#define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xD914C103 104#define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xD9150105 106#define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET 0xD9154107 108#define mmMME_CMDQ_CP_FENCE0_RDATA 0xD9158109 110#define mmMME_CMDQ_CP_FENCE1_RDATA 0xD915C111 112#define mmMME_CMDQ_CP_FENCE2_RDATA 0xD9160113 114#define mmMME_CMDQ_CP_FENCE3_RDATA 0xD9164115 116#define mmMME_CMDQ_CP_FENCE0_CNT 0xD9168117 118#define mmMME_CMDQ_CP_FENCE1_CNT 0xD916C119 120#define mmMME_CMDQ_CP_FENCE2_CNT 0xD9170121 122#define mmMME_CMDQ_CP_FENCE3_CNT 0xD9174123 124#define mmMME_CMDQ_CP_STS 0xD9178125 126#define mmMME_CMDQ_CP_CURRENT_INST_LO 0xD917C127 128#define mmMME_CMDQ_CP_CURRENT_INST_HI 0xD9180129 130#define mmMME_CMDQ_CP_BARRIER_CFG 0xD9184131 132#define mmMME_CMDQ_CP_DBG_0 0xD9188133 134#define mmMME_CMDQ_CQ_BUF_ADDR 0xD9308135 136#define mmMME_CMDQ_CQ_BUF_RDATA 0xD930C137 138#endif /* ASIC_REG_MME_CMDQ_REGS_H_ */139