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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME_QM_REGS_H_14#define ASIC_REG_MME_QM_REGS_H_15 16/*17 *****************************************18 * MME_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmMME_QM_GLBL_CFG0 0xD800023 24#define mmMME_QM_GLBL_CFG1 0xD800425 26#define mmMME_QM_GLBL_PROT 0xD800827 28#define mmMME_QM_GLBL_ERR_CFG 0xD800C29 30#define mmMME_QM_GLBL_ERR_ADDR_LO 0xD801031 32#define mmMME_QM_GLBL_ERR_ADDR_HI 0xD801433 34#define mmMME_QM_GLBL_ERR_WDATA 0xD801835 36#define mmMME_QM_GLBL_SECURE_PROPS 0xD801C37 38#define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD802039 40#define mmMME_QM_GLBL_STS0 0xD802441 42#define mmMME_QM_GLBL_STS1 0xD802843 44#define mmMME_QM_PQ_BASE_LO 0xD806045 46#define mmMME_QM_PQ_BASE_HI 0xD806447 48#define mmMME_QM_PQ_SIZE 0xD806849 50#define mmMME_QM_PQ_PI 0xD806C51 52#define mmMME_QM_PQ_CI 0xD807053 54#define mmMME_QM_PQ_CFG0 0xD807455 56#define mmMME_QM_PQ_CFG1 0xD807857 58#define mmMME_QM_PQ_ARUSER 0xD807C59 60#define mmMME_QM_PQ_PUSH0 0xD808061 62#define mmMME_QM_PQ_PUSH1 0xD808463 64#define mmMME_QM_PQ_PUSH2 0xD808865 66#define mmMME_QM_PQ_PUSH3 0xD808C67 68#define mmMME_QM_PQ_STS0 0xD809069 70#define mmMME_QM_PQ_STS1 0xD809471 72#define mmMME_QM_PQ_RD_RATE_LIM_EN 0xD80A073 74#define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xD80A475 76#define mmMME_QM_PQ_RD_RATE_LIM_SAT 0xD80A877 78#define mmMME_QM_PQ_RD_RATE_LIM_TOUT 0xD80AC79 80#define mmMME_QM_CQ_CFG0 0xD80B081 82#define mmMME_QM_CQ_CFG1 0xD80B483 84#define mmMME_QM_CQ_ARUSER 0xD80B885 86#define mmMME_QM_CQ_PTR_LO 0xD80C087 88#define mmMME_QM_CQ_PTR_HI 0xD80C489 90#define mmMME_QM_CQ_TSIZE 0xD80C891 92#define mmMME_QM_CQ_CTL 0xD80CC93 94#define mmMME_QM_CQ_PTR_LO_STS 0xD80D495 96#define mmMME_QM_CQ_PTR_HI_STS 0xD80D897 98#define mmMME_QM_CQ_TSIZE_STS 0xD80DC99 100#define mmMME_QM_CQ_CTL_STS 0xD80E0101 102#define mmMME_QM_CQ_STS0 0xD80E4103 104#define mmMME_QM_CQ_STS1 0xD80E8105 106#define mmMME_QM_CQ_RD_RATE_LIM_EN 0xD80F0107 108#define mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xD80F4109 110#define mmMME_QM_CQ_RD_RATE_LIM_SAT 0xD80F8111 112#define mmMME_QM_CQ_RD_RATE_LIM_TOUT 0xD80FC113 114#define mmMME_QM_CQ_IFIFO_CNT 0xD8108115 116#define mmMME_QM_CP_MSG_BASE0_ADDR_LO 0xD8120117 118#define mmMME_QM_CP_MSG_BASE0_ADDR_HI 0xD8124119 120#define mmMME_QM_CP_MSG_BASE1_ADDR_LO 0xD8128121 122#define mmMME_QM_CP_MSG_BASE1_ADDR_HI 0xD812C123 124#define mmMME_QM_CP_MSG_BASE2_ADDR_LO 0xD8130125 126#define mmMME_QM_CP_MSG_BASE2_ADDR_HI 0xD8134127 128#define mmMME_QM_CP_MSG_BASE3_ADDR_LO 0xD8138129 130#define mmMME_QM_CP_MSG_BASE3_ADDR_HI 0xD813C131 132#define mmMME_QM_CP_LDMA_TSIZE_OFFSET 0xD8140133 134#define mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xD8144135 136#define mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xD8148137 138#define mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xD814C139 140#define mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xD8150141 142#define mmMME_QM_CP_LDMA_COMMIT_OFFSET 0xD8154143 144#define mmMME_QM_CP_FENCE0_RDATA 0xD8158145 146#define mmMME_QM_CP_FENCE1_RDATA 0xD815C147 148#define mmMME_QM_CP_FENCE2_RDATA 0xD8160149 150#define mmMME_QM_CP_FENCE3_RDATA 0xD8164151 152#define mmMME_QM_CP_FENCE0_CNT 0xD8168153 154#define mmMME_QM_CP_FENCE1_CNT 0xD816C155 156#define mmMME_QM_CP_FENCE2_CNT 0xD8170157 158#define mmMME_QM_CP_FENCE3_CNT 0xD8174159 160#define mmMME_QM_CP_STS 0xD8178161 162#define mmMME_QM_CP_CURRENT_INST_LO 0xD817C163 164#define mmMME_QM_CP_CURRENT_INST_HI 0xD8180165 166#define mmMME_QM_CP_BARRIER_CFG 0xD8184167 168#define mmMME_QM_CP_DBG_0 0xD8188169 170#define mmMME_QM_PQ_BUF_ADDR 0xD8300171 172#define mmMME_QM_PQ_BUF_RDATA 0xD8304173 174#define mmMME_QM_CQ_BUF_ADDR 0xD8308175 176#define mmMME_QM_CQ_BUF_RDATA 0xD830C177 178#endif /* ASIC_REG_MME_QM_REGS_H_ */179