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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MMU_MASKS_H_14#define ASIC_REG_MMU_MASKS_H_15 16/*17 *****************************************18 * MMU (Prototype: MMU)19 *****************************************20 */21 22/* MMU_INPUT_FIFO_THRESHOLD */23#define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 024#define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x725#define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 426#define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x7027#define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 828#define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x70029#define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 1230#define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x700031#define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 1632#define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x7000033#define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 2034#define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x70000035#define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 2436#define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x700000037 38/* MMU_MMU_ENABLE */39#define MMU_MMU_ENABLE_R_SHIFT 040#define MMU_MMU_ENABLE_R_MASK 0x141 42/* MMU_FORCE_ORDERING */43#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 044#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x145#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 146#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x247#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 248#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x449#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 350#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x851#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 452#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x1053#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 554#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x2055#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 656#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x4057#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 858#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x10059#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 960#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x20061#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 1062#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x40063#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 1164#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x80065#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 1266#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x100067#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 1368#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x200069#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 1470#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x400071 72/* MMU_FEATURE_ENABLE */73#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 074#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x175#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 176#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x277#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 278#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x479#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 380#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x881#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 482#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x1083#define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 584#define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x2085 86/* MMU_VA_ORDERING_MASK_31_7 */87#define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 088#define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF89 90/* MMU_VA_ORDERING_MASK_49_32 */91#define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 092#define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF93 94/* MMU_LOG2_DDR_SIZE */95#define MMU_LOG2_DDR_SIZE_R_SHIFT 096#define MMU_LOG2_DDR_SIZE_R_MASK 0xFF97 98/* MMU_SCRAMBLER */99#define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0100#define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F101#define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6102#define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40103#define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7104#define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80105 106/* MMU_MEM_INIT_BUSY */107#define MMU_MEM_INIT_BUSY_DATA_SHIFT 0108#define MMU_MEM_INIT_BUSY_DATA_MASK 0x3109#define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2110#define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4111#define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3112#define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8113 114/* MMU_SPI_MASK */115#define MMU_SPI_MASK_R_SHIFT 0116#define MMU_SPI_MASK_R_MASK 0xFF117 118/* MMU_SPI_CAUSE */119#define MMU_SPI_CAUSE_R_SHIFT 0120#define MMU_SPI_CAUSE_R_MASK 0xFF121 122/* MMU_PAGE_ERROR_CAPTURE */123#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0124#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF125#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18126#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000127 128/* MMU_PAGE_ERROR_CAPTURE_VA */129#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0130#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF131 132/* MMU_ACCESS_ERROR_CAPTURE */133#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0134#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF135#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18136#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000137 138/* MMU_ACCESS_ERROR_CAPTURE_VA */139#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0140#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF141 142#endif /* ASIC_REG_MMU_MASKS_H_ */143