209 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PCI_NRTR_MASKS_H_14#define ASIC_REG_PCI_NRTR_MASKS_H_15 16/*17 *****************************************18 * PCI_NRTR (Prototype: IF_NRTR)19 *****************************************20 */21 22/* PCI_NRTR_HBW_MAX_CRED */23#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 024#define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F25#define PCI_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 826#define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F0027#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 1628#define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F000029#define PCI_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 2430#define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F00000031 32/* PCI_NRTR_LBW_MAX_CRED */33#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 034#define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F35#define PCI_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 836#define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F0037#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 1638#define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F000039#define PCI_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 2440#define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F00000041 42/* PCI_NRTR_DBG_E_ARB */43#define PCI_NRTR_DBG_E_ARB_W_SHIFT 044#define PCI_NRTR_DBG_E_ARB_W_MASK 0x745#define PCI_NRTR_DBG_E_ARB_S_SHIFT 846#define PCI_NRTR_DBG_E_ARB_S_MASK 0x70047#define PCI_NRTR_DBG_E_ARB_N_SHIFT 1648#define PCI_NRTR_DBG_E_ARB_N_MASK 0x7000049#define PCI_NRTR_DBG_E_ARB_L_SHIFT 2450#define PCI_NRTR_DBG_E_ARB_L_MASK 0x700000051 52/* PCI_NRTR_DBG_W_ARB */53#define PCI_NRTR_DBG_W_ARB_E_SHIFT 054#define PCI_NRTR_DBG_W_ARB_E_MASK 0x755#define PCI_NRTR_DBG_W_ARB_S_SHIFT 856#define PCI_NRTR_DBG_W_ARB_S_MASK 0x70057#define PCI_NRTR_DBG_W_ARB_N_SHIFT 1658#define PCI_NRTR_DBG_W_ARB_N_MASK 0x7000059#define PCI_NRTR_DBG_W_ARB_L_SHIFT 2460#define PCI_NRTR_DBG_W_ARB_L_MASK 0x700000061 62/* PCI_NRTR_DBG_N_ARB */63#define PCI_NRTR_DBG_N_ARB_W_SHIFT 064#define PCI_NRTR_DBG_N_ARB_W_MASK 0x765#define PCI_NRTR_DBG_N_ARB_E_SHIFT 866#define PCI_NRTR_DBG_N_ARB_E_MASK 0x70067#define PCI_NRTR_DBG_N_ARB_S_SHIFT 1668#define PCI_NRTR_DBG_N_ARB_S_MASK 0x7000069#define PCI_NRTR_DBG_N_ARB_L_SHIFT 2470#define PCI_NRTR_DBG_N_ARB_L_MASK 0x700000071 72/* PCI_NRTR_DBG_S_ARB */73#define PCI_NRTR_DBG_S_ARB_W_SHIFT 074#define PCI_NRTR_DBG_S_ARB_W_MASK 0x775#define PCI_NRTR_DBG_S_ARB_E_SHIFT 876#define PCI_NRTR_DBG_S_ARB_E_MASK 0x70077#define PCI_NRTR_DBG_S_ARB_N_SHIFT 1678#define PCI_NRTR_DBG_S_ARB_N_MASK 0x7000079#define PCI_NRTR_DBG_S_ARB_L_SHIFT 2480#define PCI_NRTR_DBG_S_ARB_L_MASK 0x700000081 82/* PCI_NRTR_DBG_L_ARB */83#define PCI_NRTR_DBG_L_ARB_W_SHIFT 084#define PCI_NRTR_DBG_L_ARB_W_MASK 0x785#define PCI_NRTR_DBG_L_ARB_E_SHIFT 886#define PCI_NRTR_DBG_L_ARB_E_MASK 0x70087#define PCI_NRTR_DBG_L_ARB_S_SHIFT 1688#define PCI_NRTR_DBG_L_ARB_S_MASK 0x7000089#define PCI_NRTR_DBG_L_ARB_N_SHIFT 2490#define PCI_NRTR_DBG_L_ARB_N_MASK 0x700000091 92/* PCI_NRTR_DBG_E_ARB_MAX */93#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 094#define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F95 96/* PCI_NRTR_DBG_W_ARB_MAX */97#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 098#define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F99 100/* PCI_NRTR_DBG_N_ARB_MAX */101#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0102#define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F103 104/* PCI_NRTR_DBG_S_ARB_MAX */105#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0106#define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F107 108/* PCI_NRTR_DBG_L_ARB_MAX */109#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0110#define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F111 112/* PCI_NRTR_SPLIT_COEF */113#define PCI_NRTR_SPLIT_COEF_VAL_SHIFT 0114#define PCI_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF115 116/* PCI_NRTR_SPLIT_CFG */117#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0118#define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1119#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1120#define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2121#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2122#define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC123#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4124#define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10125#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5126#define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20127#define PCI_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6128#define PCI_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0129 130/* PCI_NRTR_SPLIT_RD_SAT */131#define PCI_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0132#define PCI_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF133 134/* PCI_NRTR_SPLIT_RD_RST_TOKEN */135#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0136#define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF137 138/* PCI_NRTR_SPLIT_RD_TIMEOUT */139#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0140#define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF141 142/* PCI_NRTR_SPLIT_WR_SAT */143#define PCI_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0144#define PCI_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF145 146/* PCI_NRTR_WPLIT_WR_TST_TOLEN */147#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0148#define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF149 150/* PCI_NRTR_SPLIT_WR_TIMEOUT */151#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0152#define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF153 154/* PCI_NRTR_HBW_RANGE_HIT */155#define PCI_NRTR_HBW_RANGE_HIT_IND_SHIFT 0156#define PCI_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF157 158/* PCI_NRTR_HBW_RANGE_MASK_L */159#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0160#define PCI_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF161 162/* PCI_NRTR_HBW_RANGE_MASK_H */163#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0164#define PCI_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF165 166/* PCI_NRTR_HBW_RANGE_BASE_L */167#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0168#define PCI_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF169 170/* PCI_NRTR_HBW_RANGE_BASE_H */171#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0172#define PCI_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF173 174/* PCI_NRTR_LBW_RANGE_HIT */175#define PCI_NRTR_LBW_RANGE_HIT_IND_SHIFT 0176#define PCI_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF177 178/* PCI_NRTR_LBW_RANGE_MASK */179#define PCI_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0180#define PCI_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF181 182/* PCI_NRTR_LBW_RANGE_BASE */183#define PCI_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0184#define PCI_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF185 186/* PCI_NRTR_RGLTR */187#define PCI_NRTR_RGLTR_WR_EN_SHIFT 0188#define PCI_NRTR_RGLTR_WR_EN_MASK 0x1189#define PCI_NRTR_RGLTR_RD_EN_SHIFT 4190#define PCI_NRTR_RGLTR_RD_EN_MASK 0x10191 192/* PCI_NRTR_RGLTR_WR_RESULT */193#define PCI_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0194#define PCI_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF195 196/* PCI_NRTR_RGLTR_RD_RESULT */197#define PCI_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0198#define PCI_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF199 200/* PCI_NRTR_SCRAMB_EN */201#define PCI_NRTR_SCRAMB_EN_VAL_SHIFT 0202#define PCI_NRTR_SCRAMB_EN_VAL_MASK 0x1203 204/* PCI_NRTR_NON_LIN_SCRAMB */205#define PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0206#define PCI_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1207 208#endif /* ASIC_REG_PCI_NRTR_MASKS_H_ */209