227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PCI_NRTR_REGS_H_14#define ASIC_REG_PCI_NRTR_REGS_H_15 16/*17 *****************************************18 * PCI_NRTR (Prototype: IF_NRTR)19 *****************************************20 */21 22#define mmPCI_NRTR_HBW_MAX_CRED 0x10023 24#define mmPCI_NRTR_LBW_MAX_CRED 0x12025 26#define mmPCI_NRTR_DBG_E_ARB 0x30027 28#define mmPCI_NRTR_DBG_W_ARB 0x30429 30#define mmPCI_NRTR_DBG_N_ARB 0x30831 32#define mmPCI_NRTR_DBG_S_ARB 0x30C33 34#define mmPCI_NRTR_DBG_L_ARB 0x31035 36#define mmPCI_NRTR_DBG_E_ARB_MAX 0x32037 38#define mmPCI_NRTR_DBG_W_ARB_MAX 0x32439 40#define mmPCI_NRTR_DBG_N_ARB_MAX 0x32841 42#define mmPCI_NRTR_DBG_S_ARB_MAX 0x32C43 44#define mmPCI_NRTR_DBG_L_ARB_MAX 0x33045 46#define mmPCI_NRTR_SPLIT_COEF_0 0x40047 48#define mmPCI_NRTR_SPLIT_COEF_1 0x40449 50#define mmPCI_NRTR_SPLIT_COEF_2 0x40851 52#define mmPCI_NRTR_SPLIT_COEF_3 0x40C53 54#define mmPCI_NRTR_SPLIT_COEF_4 0x41055 56#define mmPCI_NRTR_SPLIT_COEF_5 0x41457 58#define mmPCI_NRTR_SPLIT_COEF_6 0x41859 60#define mmPCI_NRTR_SPLIT_COEF_7 0x41C61 62#define mmPCI_NRTR_SPLIT_COEF_8 0x42063 64#define mmPCI_NRTR_SPLIT_COEF_9 0x42465 66#define mmPCI_NRTR_SPLIT_CFG 0x44067 68#define mmPCI_NRTR_SPLIT_RD_SAT 0x44469 70#define mmPCI_NRTR_SPLIT_RD_RST_TOKEN 0x44871 72#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0 0x44C73 74#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1 0x45075 76#define mmPCI_NRTR_SPLIT_WR_SAT 0x45477 78#define mmPCI_NRTR_WPLIT_WR_TST_TOLEN 0x45879 80#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0 0x45C81 82#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1 0x46083 84#define mmPCI_NRTR_HBW_RANGE_HIT 0x47085 86#define mmPCI_NRTR_HBW_RANGE_MASK_L_0 0x48087 88#define mmPCI_NRTR_HBW_RANGE_MASK_L_1 0x48489 90#define mmPCI_NRTR_HBW_RANGE_MASK_L_2 0x48891 92#define mmPCI_NRTR_HBW_RANGE_MASK_L_3 0x48C93 94#define mmPCI_NRTR_HBW_RANGE_MASK_L_4 0x49095 96#define mmPCI_NRTR_HBW_RANGE_MASK_L_5 0x49497 98#define mmPCI_NRTR_HBW_RANGE_MASK_L_6 0x49899 100#define mmPCI_NRTR_HBW_RANGE_MASK_L_7 0x49C101 102#define mmPCI_NRTR_HBW_RANGE_MASK_H_0 0x4A0103 104#define mmPCI_NRTR_HBW_RANGE_MASK_H_1 0x4A4105 106#define mmPCI_NRTR_HBW_RANGE_MASK_H_2 0x4A8107 108#define mmPCI_NRTR_HBW_RANGE_MASK_H_3 0x4AC109 110#define mmPCI_NRTR_HBW_RANGE_MASK_H_4 0x4B0111 112#define mmPCI_NRTR_HBW_RANGE_MASK_H_5 0x4B4113 114#define mmPCI_NRTR_HBW_RANGE_MASK_H_6 0x4B8115 116#define mmPCI_NRTR_HBW_RANGE_MASK_H_7 0x4BC117 118#define mmPCI_NRTR_HBW_RANGE_BASE_L_0 0x4C0119 120#define mmPCI_NRTR_HBW_RANGE_BASE_L_1 0x4C4121 122#define mmPCI_NRTR_HBW_RANGE_BASE_L_2 0x4C8123 124#define mmPCI_NRTR_HBW_RANGE_BASE_L_3 0x4CC125 126#define mmPCI_NRTR_HBW_RANGE_BASE_L_4 0x4D0127 128#define mmPCI_NRTR_HBW_RANGE_BASE_L_5 0x4D4129 130#define mmPCI_NRTR_HBW_RANGE_BASE_L_6 0x4D8131 132#define mmPCI_NRTR_HBW_RANGE_BASE_L_7 0x4DC133 134#define mmPCI_NRTR_HBW_RANGE_BASE_H_0 0x4E0135 136#define mmPCI_NRTR_HBW_RANGE_BASE_H_1 0x4E4137 138#define mmPCI_NRTR_HBW_RANGE_BASE_H_2 0x4E8139 140#define mmPCI_NRTR_HBW_RANGE_BASE_H_3 0x4EC141 142#define mmPCI_NRTR_HBW_RANGE_BASE_H_4 0x4F0143 144#define mmPCI_NRTR_HBW_RANGE_BASE_H_5 0x4F4145 146#define mmPCI_NRTR_HBW_RANGE_BASE_H_6 0x4F8147 148#define mmPCI_NRTR_HBW_RANGE_BASE_H_7 0x4FC149 150#define mmPCI_NRTR_LBW_RANGE_HIT 0x500151 152#define mmPCI_NRTR_LBW_RANGE_MASK_0 0x510153 154#define mmPCI_NRTR_LBW_RANGE_MASK_1 0x514155 156#define mmPCI_NRTR_LBW_RANGE_MASK_2 0x518157 158#define mmPCI_NRTR_LBW_RANGE_MASK_3 0x51C159 160#define mmPCI_NRTR_LBW_RANGE_MASK_4 0x520161 162#define mmPCI_NRTR_LBW_RANGE_MASK_5 0x524163 164#define mmPCI_NRTR_LBW_RANGE_MASK_6 0x528165 166#define mmPCI_NRTR_LBW_RANGE_MASK_7 0x52C167 168#define mmPCI_NRTR_LBW_RANGE_MASK_8 0x530169 170#define mmPCI_NRTR_LBW_RANGE_MASK_9 0x534171 172#define mmPCI_NRTR_LBW_RANGE_MASK_10 0x538173 174#define mmPCI_NRTR_LBW_RANGE_MASK_11 0x53C175 176#define mmPCI_NRTR_LBW_RANGE_MASK_12 0x540177 178#define mmPCI_NRTR_LBW_RANGE_MASK_13 0x544179 180#define mmPCI_NRTR_LBW_RANGE_MASK_14 0x548181 182#define mmPCI_NRTR_LBW_RANGE_MASK_15 0x54C183 184#define mmPCI_NRTR_LBW_RANGE_BASE_0 0x550185 186#define mmPCI_NRTR_LBW_RANGE_BASE_1 0x554187 188#define mmPCI_NRTR_LBW_RANGE_BASE_2 0x558189 190#define mmPCI_NRTR_LBW_RANGE_BASE_3 0x55C191 192#define mmPCI_NRTR_LBW_RANGE_BASE_4 0x560193 194#define mmPCI_NRTR_LBW_RANGE_BASE_5 0x564195 196#define mmPCI_NRTR_LBW_RANGE_BASE_6 0x568197 198#define mmPCI_NRTR_LBW_RANGE_BASE_7 0x56C199 200#define mmPCI_NRTR_LBW_RANGE_BASE_8 0x570201 202#define mmPCI_NRTR_LBW_RANGE_BASE_9 0x574203 204#define mmPCI_NRTR_LBW_RANGE_BASE_10 0x578205 206#define mmPCI_NRTR_LBW_RANGE_BASE_11 0x57C207 208#define mmPCI_NRTR_LBW_RANGE_BASE_12 0x580209 210#define mmPCI_NRTR_LBW_RANGE_BASE_13 0x584211 212#define mmPCI_NRTR_LBW_RANGE_BASE_14 0x588213 214#define mmPCI_NRTR_LBW_RANGE_BASE_15 0x58C215 216#define mmPCI_NRTR_RGLTR 0x590217 218#define mmPCI_NRTR_RGLTR_WR_RESULT 0x594219 220#define mmPCI_NRTR_RGLTR_RD_RESULT 0x598221 222#define mmPCI_NRTR_SCRAMB_EN 0x600223 224#define mmPCI_NRTR_NON_LIN_SCRAMB 0x604225 226#endif /* ASIC_REG_PCI_NRTR_REGS_H_ */227