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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_PSOC_SPI_REGS_H_14#define ASIC_REG_PSOC_SPI_REGS_H_15 16/*17 *****************************************18 * PSOC_SPI (Prototype: SPI)19 *****************************************20 */21 22#define mmPSOC_SPI_CTRLR0 0xC4300023 24#define mmPSOC_SPI_CTRLR1 0xC4300425 26#define mmPSOC_SPI_SSIENR 0xC4300827 28#define mmPSOC_SPI_MWCR 0xC4300C29 30#define mmPSOC_SPI_SER 0xC4301031 32#define mmPSOC_SPI_BAUDR 0xC4301433 34#define mmPSOC_SPI_TXFTLR 0xC4301835 36#define mmPSOC_SPI_RXFTLR 0xC4301C37 38#define mmPSOC_SPI_TXFLR 0xC4302039 40#define mmPSOC_SPI_RXFLR 0xC4302441 42#define mmPSOC_SPI_SR 0xC4302843 44#define mmPSOC_SPI_IMR 0xC4302C45 46#define mmPSOC_SPI_ISR 0xC4303047 48#define mmPSOC_SPI_RISR 0xC4303449 50#define mmPSOC_SPI_TXOICR 0xC4303851 52#define mmPSOC_SPI_RXOICR 0xC4303C53 54#define mmPSOC_SPI_RXUICR 0xC4304055 56#define mmPSOC_SPI_MSTICR 0xC4304457 58#define mmPSOC_SPI_ICR 0xC4304859 60#define mmPSOC_SPI_IDR 0xC4305861 62#define mmPSOC_SPI_SSI_VERSION_ID 0xC4305C63 64#define mmPSOC_SPI_DR0 0xC4306065 66#define mmPSOC_SPI_DR1 0xC4306467 68#define mmPSOC_SPI_DR2 0xC4306869 70#define mmPSOC_SPI_DR3 0xC4306C71 72#define mmPSOC_SPI_DR4 0xC4307073 74#define mmPSOC_SPI_DR5 0xC4307475 76#define mmPSOC_SPI_DR6 0xC4307877 78#define mmPSOC_SPI_DR7 0xC4307C79 80#define mmPSOC_SPI_DR8 0xC4308081 82#define mmPSOC_SPI_DR9 0xC4308483 84#define mmPSOC_SPI_DR10 0xC4308885 86#define mmPSOC_SPI_DR11 0xC4308C87 88#define mmPSOC_SPI_DR12 0xC4309089 90#define mmPSOC_SPI_DR13 0xC4309491 92#define mmPSOC_SPI_DR14 0xC4309893 94#define mmPSOC_SPI_DR15 0xC4309C95 96#define mmPSOC_SPI_DR16 0xC430A097 98#define mmPSOC_SPI_DR17 0xC430A499 100#define mmPSOC_SPI_DR18 0xC430A8101 102#define mmPSOC_SPI_DR19 0xC430AC103 104#define mmPSOC_SPI_DR20 0xC430B0105 106#define mmPSOC_SPI_DR21 0xC430B4107 108#define mmPSOC_SPI_DR22 0xC430B8109 110#define mmPSOC_SPI_DR23 0xC430BC111 112#define mmPSOC_SPI_DR24 0xC430C0113 114#define mmPSOC_SPI_DR25 0xC430C4115 116#define mmPSOC_SPI_DR26 0xC430C8117 118#define mmPSOC_SPI_DR27 0xC430CC119 120#define mmPSOC_SPI_DR28 0xC430D0121 122#define mmPSOC_SPI_DR29 0xC430D4123 124#define mmPSOC_SPI_DR30 0xC430D8125 126#define mmPSOC_SPI_DR31 0xC430DC127 128#define mmPSOC_SPI_DR32 0xC430E0129 130#define mmPSOC_SPI_DR33 0xC430E4131 132#define mmPSOC_SPI_DR34 0xC430E8133 134#define mmPSOC_SPI_DR35 0xC430EC135 136#define mmPSOC_SPI_RX_SAMPLE_DLY 0xC430F0137 138#define mmPSOC_SPI_RSVD_1 0xC430F8139 140#define mmPSOC_SPI_RSVD_2 0xC430FC141 142#endif /* ASIC_REG_PSOC_SPI_REGS_H_ */143