1607 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_CFG_MASKS_H_14#define ASIC_REG_TPC0_CFG_MASKS_H_15 16/*17 *****************************************18 * TPC0_CFG (Prototype: TPC)19 *****************************************20 */21 22/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */23#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 024#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF25 26/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */27#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 028#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF29 30/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */31#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 032#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF33 34/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */35#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 036#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x337#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 838#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F0039#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 1640#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x7000041 42/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */43#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 044#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF45 46/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */47#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 048#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF49 50/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET */51#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 052#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF53 54/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */55#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 056#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF57 58/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */59#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 060#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF61 62/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET */63#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 064#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF65 66/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */67#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 068#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF69 70/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */71#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 072#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF73 74/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET */75#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 076#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF77 78/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */79#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 080#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF81 82/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */83#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 084#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF85 86/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET */87#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 088#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF89 90/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */91#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 092#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF93 94/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */95#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 096#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF97 98/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET */99#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0100#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF101 102/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */103#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0104#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF105 106/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */107#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0108#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF109 110/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */111#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0112#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF113 114/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */115#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0116#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3117#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8118#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00119#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16120#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000121 122/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */123#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0124#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF125 126/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */127#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0128#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF129 130/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET */131#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0132#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF133 134/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */135#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0136#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF137 138/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */139#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0140#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF141 142/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET */143#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0144#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF145 146/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */147#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0148#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF149 150/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */151#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0152#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF153 154/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET */155#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0156#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF157 158/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */159#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0160#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF161 162/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */163#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0164#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF165 166/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET */167#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0168#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF169 170/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */171#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0172#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF173 174/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */175#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0176#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF177 178/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET */179#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 0180#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF181 182/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */183#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0184#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF185 186/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */187#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0188#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF189 190/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */191#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0192#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF193 194/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */195#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0196#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x3197#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8198#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00199#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16200#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000201 202/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */203#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0204#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF205 206/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */207#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0208#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF209 210/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET */211#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 0212#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF213 214/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */215#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0216#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF217 218/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */219#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0220#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF221 222/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET */223#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 0224#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF225 226/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */227#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0228#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF229 230/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */231#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0232#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF233 234/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET */235#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 0236#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF237 238/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */239#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0240#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF241 242/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */243#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0244#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF245 246/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET */247#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 0248#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF249 250/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */251#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0252#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF253 254/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */255#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0256#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF257 258/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET */259#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 0260#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF261 262/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */263#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0264#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF265 266/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */267#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0268#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF269 270/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */271#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0272#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF273 274/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */275#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0276#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x3277#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8278#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00279#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16280#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000281 282/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */283#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0284#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF285 286/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */287#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0288#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF289 290/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET */291#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 0292#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF293 294/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */295#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0296#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF297 298/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */299#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0300#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF301 302/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET */303#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 0304#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF305 306/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */307#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0308#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF309 310/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */311#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0312#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF313 314/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET */315#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 0316#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF317 318/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */319#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0320#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF321 322/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */323#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0324#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF325 326/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET */327#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 0328#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF329 330/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */331#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0332#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF333 334/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */335#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0336#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF337 338/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET */339#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 0340#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF341 342/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */343#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0344#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF345 346/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */347#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0348#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF349 350/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */351#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0352#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF353 354/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */355#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0356#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x3357#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8358#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00359#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16360#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000361 362/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */363#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0364#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF365 366/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */367#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0368#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF369 370/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET */371#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 0372#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF373 374/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */375#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0376#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF377 378/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */379#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0380#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF381 382/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET */383#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 0384#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF385 386/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */387#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0388#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF389 390/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */391#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0392#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF393 394/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET */395#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 0396#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF397 398/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */399#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0400#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF401 402/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */403#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0404#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF405 406/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET */407#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 0408#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF409 410/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */411#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0412#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF413 414/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */415#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0416#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF417 418/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET */419#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 0420#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF421 422/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */423#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0424#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF425 426/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */427#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0428#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF429 430/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */431#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0432#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF433 434/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */435#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0436#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x3437#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8438#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00439#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16440#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000441 442/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */443#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0444#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF445 446/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */447#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0448#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF449 450/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET */451#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 0452#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF453 454/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */455#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0456#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF457 458/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */459#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0460#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF461 462/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET */463#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 0464#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF465 466/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */467#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0468#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF469 470/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */471#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0472#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF473 474/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET */475#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 0476#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF477 478/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */479#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0480#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF481 482/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */483#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0484#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF485 486/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET */487#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 0488#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF489 490/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */491#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0492#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF493 494/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */495#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0496#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF497 498/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET */499#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 0500#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF501 502/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */503#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0504#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF505 506/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */507#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0508#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF509 510/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */511#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0512#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF513 514/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */515#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0516#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x3517#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8518#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00519#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16520#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000521 522/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */523#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0524#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF525 526/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */527#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0528#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF529 530/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET */531#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 0532#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF533 534/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */535#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0536#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF537 538/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */539#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0540#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF541 542/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET */543#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 0544#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF545 546/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */547#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0548#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF549 550/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */551#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0552#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF553 554/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET */555#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 0556#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF557 558/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */559#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0560#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF561 562/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */563#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0564#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF565 566/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET */567#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 0568#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF569 570/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */571#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0572#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF573 574/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */575#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0576#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF577 578/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET */579#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 0580#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF581 582/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */583#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0584#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF585 586/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */587#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0588#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF589 590/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */591#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0592#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF593 594/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */595#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0596#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x3597#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8598#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00599#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16600#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000601 602/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */603#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0604#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF605 606/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */607#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0608#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF609 610/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET */611#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 0612#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF613 614/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */615#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0616#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF617 618/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */619#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0620#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF621 622/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET */623#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 0624#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF625 626/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */627#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0628#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF629 630/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */631#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0632#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF633 634/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET */635#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 0636#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF637 638/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */639#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0640#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF641 642/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */643#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0644#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF645 646/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET */647#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 0648#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF649 650/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */651#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0652#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF653 654/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */655#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0656#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF657 658/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET */659#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 0660#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF661 662/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */663#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0664#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF665 666/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */667#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0668#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF669 670/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */671#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0672#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF673 674/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */675#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0676#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF677 678/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */679#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0680#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF681 682/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */683#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0684#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF685 686/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */687#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0688#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF689 690/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */691#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0692#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF693 694/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */695#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0696#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF697 698/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */699#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0700#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF701 702/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */703#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0704#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF705 706/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */707#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0708#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF709 710/* TPC0_CFG_KERNEL_SRF */711#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0712#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF713 714/* TPC0_CFG_KERNEL_KERNEL_CONFIG */715#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0716#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1717#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1718#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2719#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 8720#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F00721 722/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */723#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0724#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF725#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 16726#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF0000727#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 31728#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x80000000729 730/* TPC0_CFG_RESERVED_DESC_END */731#define TPC0_CFG_RESERVED_DESC_END_V_SHIFT 0732#define TPC0_CFG_RESERVED_DESC_END_V_MASK 0xFFFFFFFF733 734/* TPC0_CFG_ROUND_CSR */735#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0736#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7737 738/* TPC0_CFG_TBUF_BASE_ADDR_LOW */739#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT 0740#define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF741 742/* TPC0_CFG_TBUF_BASE_ADDR_HIGH */743#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT 0744#define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF745 746/* TPC0_CFG_SEMAPHORE */747#define TPC0_CFG_SEMAPHORE_V_SHIFT 0748#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF749 750/* TPC0_CFG_VFLAGS */751#define TPC0_CFG_VFLAGS_V_SHIFT 0752#define TPC0_CFG_VFLAGS_V_MASK 0xF753 754/* TPC0_CFG_SFLAGS */755#define TPC0_CFG_SFLAGS_V_SHIFT 0756#define TPC0_CFG_SFLAGS_V_MASK 0xF757 758/* TPC0_CFG_LFSR_POLYNOM */759#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0760#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF761 762/* TPC0_CFG_STATUS */763#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1764#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2765#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2766#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4767#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3768#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8769#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT 4770#define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK 0x10771 772/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */773#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0774#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF775 776/* TPC0_CFG_CFG_SUBTRACT_VALUE */777#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0778#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF779 780/* TPC0_CFG_SM_BASE_ADDRESS_LOW */781#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT 0782#define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF783 784/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */785#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0786#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF787 788/* TPC0_CFG_TPC_CMD */789#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0790#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1791#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1792#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2793#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2794#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4795#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3796#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8797#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4798#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10799#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5800#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20801#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6802#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40803 804/* TPC0_CFG_TPC_EXECUTE */805#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0806#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1807 808/* TPC0_CFG_TPC_STALL */809#define TPC0_CFG_TPC_STALL_V_SHIFT 0810#define TPC0_CFG_TPC_STALL_V_MASK 0x1811 812/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */813#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0814#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF815 816/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */817#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0818#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF819 820/* TPC0_CFG_MSS_CONFIG */821#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0822#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF823#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4824#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0825#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8826#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300827#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10828#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400829 830/* TPC0_CFG_TPC_INTR_CAUSE */831#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0832#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF833 834/* TPC0_CFG_TPC_INTR_MASK */835#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0836#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF837 838/* TPC0_CFG_TSB_CONFIG */839#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT 0840#define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK 0x1F841#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT 5842#define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK 0x3E0843#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT 10844#define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK 0xFFC00845#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT 20846#define TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK 0x3FF00000847 848/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */849#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0850#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF851 852/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */853#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0854#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF855 856/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */857#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0858#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF859 860/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */861#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0862#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3863#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8864#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00865#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16866#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000867 868/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */869#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0870#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF871 872/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */873#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0874#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF875 876/* TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET */877#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT 0878#define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF879 880/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */881#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0882#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF883 884/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */885#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0886#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF887 888/* TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET */889#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT 0890#define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF891 892/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */893#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0894#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF895 896/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */897#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0898#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF899 900/* TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET */901#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT 0902#define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF903 904/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */905#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0906#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF907 908/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */909#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0910#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF911 912/* TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET */913#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT 0914#define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF915 916/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */917#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0918#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF919 920/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */921#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0922#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF923 924/* TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET */925#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT 0926#define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF927 928/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */929#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0930#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF931 932/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */933#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0934#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF935 936/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */937#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0938#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF939 940/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */941#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0942#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x3943#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8944#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00945#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16946#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000947 948/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */949#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0950#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF951 952/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */953#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0954#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF955 956/* TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET */957#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT 0958#define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF959 960/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */961#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0962#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF963 964/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */965#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0966#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF967 968/* TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET */969#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT 0970#define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF971 972/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */973#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0974#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF975 976/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */977#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0978#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF979 980/* TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET */981#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT 0982#define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF983 984/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */985#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0986#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF987 988/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */989#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0990#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF991 992/* TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET */993#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT 0994#define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF995 996/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */997#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0998#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF999 1000/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */1001#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 01002#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1003 1004/* TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET */1005#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT 01006#define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1007 1008/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */1009#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 01010#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1011 1012/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */1013#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 01014#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1015 1016/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */1017#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 01018#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF1019 1020/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */1021#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 01022#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x31023#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81024#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001025#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 161026#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x700001027 1028/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */1029#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 01030#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF1031 1032/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */1033#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 01034#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1035 1036/* TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET */1037#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT 01038#define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1039 1040/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */1041#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 01042#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF1043 1044/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */1045#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 01046#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1047 1048/* TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET */1049#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT 01050#define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1051 1052/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */1053#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 01054#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF1055 1056/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */1057#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 01058#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1059 1060/* TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET */1061#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT 01062#define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1063 1064/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */1065#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 01066#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF1067 1068/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */1069#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 01070#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1071 1072/* TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET */1073#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT 01074#define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1075 1076/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */1077#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 01078#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF1079 1080/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */1081#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 01082#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1083 1084/* TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET */1085#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT 01086#define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1087 1088/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */1089#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 01090#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1091 1092/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */1093#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 01094#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1095 1096/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */1097#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 01098#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF1099 1100/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */1101#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 01102#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x31103#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81104#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001105#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 161106#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x700001107 1108/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */1109#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 01110#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF1111 1112/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */1113#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 01114#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1115 1116/* TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET */1117#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT 01118#define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1119 1120/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */1121#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 01122#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF1123 1124/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */1125#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 01126#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1127 1128/* TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET */1129#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT 01130#define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1131 1132/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */1133#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 01134#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF1135 1136/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */1137#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 01138#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1139 1140/* TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET */1141#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT 01142#define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1143 1144/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */1145#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 01146#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF1147 1148/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */1149#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 01150#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1151 1152/* TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET */1153#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT 01154#define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1155 1156/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */1157#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 01158#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF1159 1160/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */1161#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 01162#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1163 1164/* TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET */1165#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT 01166#define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1167 1168/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */1169#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 01170#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1171 1172/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */1173#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 01174#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1175 1176/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */1177#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 01178#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF1179 1180/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */1181#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 01182#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x31183#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81184#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001185#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 161186#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x700001187 1188/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */1189#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 01190#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF1191 1192/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */1193#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 01194#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1195 1196/* TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET */1197#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT 01198#define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1199 1200/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */1201#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 01202#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF1203 1204/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */1205#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 01206#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1207 1208/* TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET */1209#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT 01210#define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1211 1212/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */1213#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 01214#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF1215 1216/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */1217#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 01218#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1219 1220/* TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET */1221#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT 01222#define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1223 1224/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */1225#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 01226#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF1227 1228/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */1229#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 01230#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1231 1232/* TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET */1233#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT 01234#define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1235 1236/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */1237#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 01238#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF1239 1240/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */1241#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 01242#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1243 1244/* TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET */1245#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT 01246#define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1247 1248/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */1249#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 01250#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1251 1252/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */1253#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 01254#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1255 1256/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */1257#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 01258#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF1259 1260/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */1261#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 01262#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x31263#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81264#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001265#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 161266#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x700001267 1268/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */1269#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 01270#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF1271 1272/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */1273#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 01274#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1275 1276/* TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET */1277#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT 01278#define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1279 1280/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */1281#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 01282#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF1283 1284/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */1285#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 01286#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1287 1288/* TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET */1289#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT 01290#define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1291 1292/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */1293#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 01294#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF1295 1296/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */1297#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 01298#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1299 1300/* TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET */1301#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT 01302#define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1303 1304/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */1305#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 01306#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF1307 1308/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */1309#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 01310#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1311 1312/* TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET */1313#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT 01314#define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1315 1316/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */1317#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 01318#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF1319 1320/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */1321#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 01322#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1323 1324/* TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET */1325#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT 01326#define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1327 1328/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */1329#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 01330#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1331 1332/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */1333#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 01334#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1335 1336/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */1337#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 01338#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF1339 1340/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */1341#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 01342#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x31343#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81344#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001345#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 161346#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x700001347 1348/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */1349#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 01350#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF1351 1352/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */1353#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 01354#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1355 1356/* TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET */1357#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT 01358#define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1359 1360/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */1361#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 01362#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF1363 1364/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */1365#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 01366#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1367 1368/* TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET */1369#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT 01370#define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1371 1372/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */1373#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 01374#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF1375 1376/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */1377#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 01378#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1379 1380/* TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET */1381#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT 01382#define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1383 1384/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */1385#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 01386#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF1387 1388/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */1389#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 01390#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1391 1392/* TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET */1393#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT 01394#define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1395 1396/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */1397#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 01398#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF1399 1400/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */1401#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 01402#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1403 1404/* TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET */1405#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT 01406#define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1407 1408/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */1409#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 01410#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1411 1412/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */1413#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 01414#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1415 1416/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */1417#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 01418#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF1419 1420/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */1421#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 01422#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x31423#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81424#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001425#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 161426#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x700001427 1428/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */1429#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 01430#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF1431 1432/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */1433#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 01434#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1435 1436/* TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET */1437#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT 01438#define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK 0xFFFFFFFF1439 1440/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */1441#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 01442#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF1443 1444/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */1445#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 01446#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1447 1448/* TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET */1449#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT 01450#define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK 0xFFFFFFFF1451 1452/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */1453#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 01454#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF1455 1456/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */1457#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 01458#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1459 1460/* TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET */1461#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT 01462#define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK 0xFFFFFFFF1463 1464/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */1465#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 01466#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF1467 1468/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */1469#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 01470#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1471 1472/* TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET */1473#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT 01474#define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK 0xFFFFFFFF1475 1476/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */1477#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 01478#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF1479 1480/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */1481#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 01482#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1483 1484/* TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET */1485#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT 01486#define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK 0xFFFFFFFF1487 1488/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */1489#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 01490#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF1491 1492/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */1493#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 01494#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF1495 1496/* TPC0_CFG_QM_TID_BASE_DIM_0 */1497#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 01498#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF1499 1500/* TPC0_CFG_QM_TID_SIZE_DIM_0 */1501#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 01502#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF1503 1504/* TPC0_CFG_QM_TID_BASE_DIM_1 */1505#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 01506#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF1507 1508/* TPC0_CFG_QM_TID_SIZE_DIM_1 */1509#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 01510#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF1511 1512/* TPC0_CFG_QM_TID_BASE_DIM_2 */1513#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 01514#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF1515 1516/* TPC0_CFG_QM_TID_SIZE_DIM_2 */1517#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 01518#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF1519 1520/* TPC0_CFG_QM_TID_BASE_DIM_3 */1521#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 01522#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF1523 1524/* TPC0_CFG_QM_TID_SIZE_DIM_3 */1525#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 01526#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF1527 1528/* TPC0_CFG_QM_TID_BASE_DIM_4 */1529#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 01530#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF1531 1532/* TPC0_CFG_QM_TID_SIZE_DIM_4 */1533#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 01534#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF1535 1536/* TPC0_CFG_QM_SRF */1537#define TPC0_CFG_QM_SRF_V_SHIFT 01538#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF1539 1540/* TPC0_CFG_QM_KERNEL_CONFIG */1541#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 01542#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x11543#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 11544#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x21545#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 81546#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0x3F001547 1548/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */1549#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 01550#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF1551#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT 161552#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK 0x7FFF00001553#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 311554#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0x800000001555 1556/* TPC0_CFG_ARUSER */1557#define TPC0_CFG_ARUSER_ASID_SHIFT 01558#define TPC0_CFG_ARUSER_ASID_MASK 0x3FF1559#define TPC0_CFG_ARUSER_MMBP_SHIFT 101560#define TPC0_CFG_ARUSER_MMBP_MASK 0x4001561#define TPC0_CFG_ARUSER_V_SHIFT 111562#define TPC0_CFG_ARUSER_V_MASK 0xFFFFF8001563 1564/* TPC0_CFG_AWUSER */1565#define TPC0_CFG_AWUSER_ASID_SHIFT 01566#define TPC0_CFG_AWUSER_ASID_MASK 0x3FF1567#define TPC0_CFG_AWUSER_MMBP_SHIFT 101568#define TPC0_CFG_AWUSER_MMBP_MASK 0x4001569#define TPC0_CFG_AWUSER_V_SHIFT 111570#define TPC0_CFG_AWUSER_V_MASK 0xFFFFF8001571 1572/* TPC0_CFG_FUNC_MBIST_CNTRL */1573#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 01574#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x11575#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 11576#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x21577#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 21578#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x41579#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 161580#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF00001581 1582/* TPC0_CFG_FUNC_MBIST_PAT */1583#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 01584#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x31585#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 21586#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC1587#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 41588#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x301589#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 61590#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC01591#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 81592#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x3001593#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 101594#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC001595 1596/* TPC0_CFG_FUNC_MBIST_MEM */1597#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 01598#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF1599#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 121600#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x70001601#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 161602#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF00001603#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 281604#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x700000001605 1606#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */1607