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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_CFG_REGS_H_14#define ASIC_REG_TPC0_CFG_REGS_H_15 16/*17 *****************************************18 * TPC0_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE0640023 24#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE0640425 26#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE0640827 28#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C29 30#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE0641031 32#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE0641433 34#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE0641835 36#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE0641C37 38#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0642039 40#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE0642441 42#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE0642843 44#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE0642C45 46#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE0643047 48#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE0643449 50#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0643851 52#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE0643C53 54#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE0644055 56#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE0644457 58#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE0644859 60#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE0644C61 62#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0645063 64#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE0645465 66#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE0645867 68#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE0645C69 70#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0646071 72#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE0646473 74#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE0646875 76#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE0646C77 78#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE0647079 80#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE0647481 82#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0647883 84#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE0647C85 86#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE0648087 88#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE0648489 90#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE0648891 92#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE0648C93 94#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0649095 96#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE0649497 98#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE0649899 100#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE0649C101 102#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE064A0103 104#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE064A4105 106#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE064A8107 108#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE064AC109 110#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE064B0111 112#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE064B4113 114#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE064B8115 116#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE064BC117 118#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE064C0119 120#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE064C4121 122#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE064C8123 124#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE064CC125 126#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE064D0127 128#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE064D4129 130#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064D8131 132#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064DC133 134#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE064E0135 136#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064E4137 138#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064E8139 140#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064EC141 142#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064F0143 144#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064F4145 146#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064F8147 148#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE064FC149 150#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE06500151 152#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE06504153 154#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE06508155 156#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE0650C157 158#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE06510159 160#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE06514161 162#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE06518163 164#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE0651C165 166#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE06520167 168#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE06524169 170#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE06528171 172#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE0652C173 174#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE06530175 176#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE06534177 178#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE06538179 180#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE0653C181 182#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE06540183 184#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE06544185 186#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE06548187 188#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE0654C189 190#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE06550191 192#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE06554193 194#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06558195 196#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE0655C197 198#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE06560199 200#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06564201 202#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE06568203 204#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE0656C205 206#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06570207 208#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06574209 210#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE06578211 212#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE0657C213 214#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE06580215 216#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06584217 218#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06588219 220#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE0658C221 222#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE06590223 224#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE06594225 226#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06598227 228#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE0659C229 230#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE065A0231 232#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE065A4233 234#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE065A8235 236#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE065AC237 238#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE065B0239 240#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE065B4241 242#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE065B8243 244#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE065BC245 246#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE065C0247 248#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE065C4249 250#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE065C8251 252#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE065CC253 254#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE065D0255 256#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE065D4257 258#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE065D8259 260#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE065DC261 262#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE065E0263 264#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE065E4265 266#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE065E8267 268#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE065EC269 270#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE065F0271 272#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE065F4273 274#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE065F8275 276#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE065FC277 278#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE06600279 280#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE06604281 282#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06608283 284#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE0660C285 286#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE06610287 288#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06614289 290#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE06618291 292#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE0661C293 294#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06620295 296#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06624297 298#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE06628299 300#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE0662C301 302#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE06630303 304#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE06634305 306#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE06638307 308#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE0663C309 310#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE06640311 312#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE06644313 314#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE06648315 316#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE0664C317 318#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE06650319 320#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE06654321 322#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE06658323 324#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE0665C325 326#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06660327 328#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE06664329 330#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06668331 332#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE0666C333 334#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06670335 336#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE06674337 338#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE06678339 340#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE0667C341 342#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE06680343 344#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE06684345 346#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE06688347 348#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE0668C349 350#define mmTPC0_CFG_KERNEL_SRF_0 0xE06690351 352#define mmTPC0_CFG_KERNEL_SRF_1 0xE06694353 354#define mmTPC0_CFG_KERNEL_SRF_2 0xE06698355 356#define mmTPC0_CFG_KERNEL_SRF_3 0xE0669C357 358#define mmTPC0_CFG_KERNEL_SRF_4 0xE066A0359 360#define mmTPC0_CFG_KERNEL_SRF_5 0xE066A4361 362#define mmTPC0_CFG_KERNEL_SRF_6 0xE066A8363 364#define mmTPC0_CFG_KERNEL_SRF_7 0xE066AC365 366#define mmTPC0_CFG_KERNEL_SRF_8 0xE066B0367 368#define mmTPC0_CFG_KERNEL_SRF_9 0xE066B4369 370#define mmTPC0_CFG_KERNEL_SRF_10 0xE066B8371 372#define mmTPC0_CFG_KERNEL_SRF_11 0xE066BC373 374#define mmTPC0_CFG_KERNEL_SRF_12 0xE066C0375 376#define mmTPC0_CFG_KERNEL_SRF_13 0xE066C4377 378#define mmTPC0_CFG_KERNEL_SRF_14 0xE066C8379 380#define mmTPC0_CFG_KERNEL_SRF_15 0xE066CC381 382#define mmTPC0_CFG_KERNEL_SRF_16 0xE066D0383 384#define mmTPC0_CFG_KERNEL_SRF_17 0xE066D4385 386#define mmTPC0_CFG_KERNEL_SRF_18 0xE066D8387 388#define mmTPC0_CFG_KERNEL_SRF_19 0xE066DC389 390#define mmTPC0_CFG_KERNEL_SRF_20 0xE066E0391 392#define mmTPC0_CFG_KERNEL_SRF_21 0xE066E4393 394#define mmTPC0_CFG_KERNEL_SRF_22 0xE066E8395 396#define mmTPC0_CFG_KERNEL_SRF_23 0xE066EC397 398#define mmTPC0_CFG_KERNEL_SRF_24 0xE066F0399 400#define mmTPC0_CFG_KERNEL_SRF_25 0xE066F4401 402#define mmTPC0_CFG_KERNEL_SRF_26 0xE066F8403 404#define mmTPC0_CFG_KERNEL_SRF_27 0xE066FC405 406#define mmTPC0_CFG_KERNEL_SRF_28 0xE06700407 408#define mmTPC0_CFG_KERNEL_SRF_29 0xE06704409 410#define mmTPC0_CFG_KERNEL_SRF_30 0xE06708411 412#define mmTPC0_CFG_KERNEL_SRF_31 0xE0670C413 414#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE06710415 416#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06714417 418#define mmTPC0_CFG_RESERVED_DESC_END 0xE06738419 420#define mmTPC0_CFG_ROUND_CSR 0xE067FC421 422#define mmTPC0_CFG_TBUF_BASE_ADDR_LOW 0xE06800423 424#define mmTPC0_CFG_TBUF_BASE_ADDR_HIGH 0xE06804425 426#define mmTPC0_CFG_SEMAPHORE 0xE06808427 428#define mmTPC0_CFG_VFLAGS 0xE0680C429 430#define mmTPC0_CFG_SFLAGS 0xE06810431 432#define mmTPC0_CFG_LFSR_POLYNOM 0xE06818433 434#define mmTPC0_CFG_STATUS 0xE0681C435 436#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06820437 438#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06824439 440#define mmTPC0_CFG_SM_BASE_ADDRESS_LOW 0xE06828441 442#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0682C443 444#define mmTPC0_CFG_TPC_CMD 0xE06830445 446#define mmTPC0_CFG_TPC_EXECUTE 0xE06838447 448#define mmTPC0_CFG_TPC_STALL 0xE0683C449 450#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06840451 452#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06844453 454#define mmTPC0_CFG_MSS_CONFIG 0xE06854455 456#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06858457 458#define mmTPC0_CFG_TPC_INTR_MASK 0xE0685C459 460#define mmTPC0_CFG_TSB_CONFIG 0xE06860461 462#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00463 464#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04465 466#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08467 468#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C469 470#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10471 472#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14473 474#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE06A18475 476#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A1C477 478#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A20479 480#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE06A24481 482#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A28483 484#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A2C485 486#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE06A30487 488#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A34489 490#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A38491 492#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE06A3C493 494#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A40495 496#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A44497 498#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE06A48499 500#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A4C501 502#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A50503 504#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A54505 506#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A58507 508#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A5C509 510#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A60511 512#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE06A64513 514#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A68515 516#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A6C517 518#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE06A70519 520#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A74521 522#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A78523 524#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE06A7C525 526#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A80527 528#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A84529 530#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE06A88531 532#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A8C533 534#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A90535 536#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE06A94537 538#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A98539 540#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A9C541 542#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06AA0543 544#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06AA4545 546#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06AA8547 548#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06AAC549 550#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE06AB0551 552#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06AB4553 554#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06AB8555 556#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE06ABC557 558#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06AC0559 560#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06AC4561 562#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE06AC8563 564#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06ACC565 566#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06AD0567 568#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE06AD4569 570#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AD8571 572#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06ADC573 574#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE06AE0575 576#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AE4577 578#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AE8579 580#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AEC581 582#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AF0583 584#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AF4585 586#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06AF8587 588#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE06AFC589 590#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06B00591 592#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06B04593 594#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE06B08595 596#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06B0C597 598#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06B10599 600#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE06B14601 602#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06B18603 604#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06B1C605 606#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE06B20607 608#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06B24609 610#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06B28611 612#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE06B2C613 614#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06B30615 616#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06B34617 618#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06B38619 620#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06B3C621 622#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06B40623 624#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06B44625 626#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE06B48627 628#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06B4C629 630#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06B50631 632#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE06B54633 634#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B58635 636#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B5C637 638#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE06B60639 640#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B64641 642#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B68643 644#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE06B6C645 646#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B70647 648#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B74649 650#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE06B78651 652#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B7C653 654#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B80655 656#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B84657 658#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B88659 660#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B8C661 662#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B90663 664#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE06B94665 666#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B98667 668#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B9C669 670#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE06BA0671 672#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06BA4673 674#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06BA8675 676#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE06BAC677 678#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06BB0679 680#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06BB4681 682#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE06BB8683 684#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06BBC685 686#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06BC0687 688#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE06BC4689 690#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06BC8691 692#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06BCC693 694#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06BD0695 696#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06BD4697 698#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06BD8699 700#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06BDC701 702#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE06BE0703 704#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06BE4705 706#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06BE8707 708#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE06BEC709 710#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06BF0711 712#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06BF4713 714#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE06BF8715 716#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06BFC717 718#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06C00719 720#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE06C04721 722#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06C08723 724#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06C0C725 726#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE06C10727 728#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06C14729 730#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06C18731 732#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06C1C733 734#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06C20735 736#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06C24737 738#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06C28739 740#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE06C2C741 742#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06C30743 744#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06C34745 746#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE06C38747 748#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06C3C749 750#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06C40751 752#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE06C44753 754#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06C48755 756#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06C4C757 758#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE06C50759 760#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06C54761 762#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06C58763 764#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE06C5C765 766#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06C60767 768#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06C64769 770#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06C68771 772#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06C6C773 774#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06C70775 776#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06C74777 778#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06C78779 780#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06C7C781 782#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06C80783 784#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06C84785 786#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06C88787 788#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06C8C789 790#define mmTPC0_CFG_QM_SRF_0 0xE06C90791 792#define mmTPC0_CFG_QM_SRF_1 0xE06C94793 794#define mmTPC0_CFG_QM_SRF_2 0xE06C98795 796#define mmTPC0_CFG_QM_SRF_3 0xE06C9C797 798#define mmTPC0_CFG_QM_SRF_4 0xE06CA0799 800#define mmTPC0_CFG_QM_SRF_5 0xE06CA4801 802#define mmTPC0_CFG_QM_SRF_6 0xE06CA8803 804#define mmTPC0_CFG_QM_SRF_7 0xE06CAC805 806#define mmTPC0_CFG_QM_SRF_8 0xE06CB0807 808#define mmTPC0_CFG_QM_SRF_9 0xE06CB4809 810#define mmTPC0_CFG_QM_SRF_10 0xE06CB8811 812#define mmTPC0_CFG_QM_SRF_11 0xE06CBC813 814#define mmTPC0_CFG_QM_SRF_12 0xE06CC0815 816#define mmTPC0_CFG_QM_SRF_13 0xE06CC4817 818#define mmTPC0_CFG_QM_SRF_14 0xE06CC8819 820#define mmTPC0_CFG_QM_SRF_15 0xE06CCC821 822#define mmTPC0_CFG_QM_SRF_16 0xE06CD0823 824#define mmTPC0_CFG_QM_SRF_17 0xE06CD4825 826#define mmTPC0_CFG_QM_SRF_18 0xE06CD8827 828#define mmTPC0_CFG_QM_SRF_19 0xE06CDC829 830#define mmTPC0_CFG_QM_SRF_20 0xE06CE0831 832#define mmTPC0_CFG_QM_SRF_21 0xE06CE4833 834#define mmTPC0_CFG_QM_SRF_22 0xE06CE8835 836#define mmTPC0_CFG_QM_SRF_23 0xE06CEC837 838#define mmTPC0_CFG_QM_SRF_24 0xE06CF0839 840#define mmTPC0_CFG_QM_SRF_25 0xE06CF4841 842#define mmTPC0_CFG_QM_SRF_26 0xE06CF8843 844#define mmTPC0_CFG_QM_SRF_27 0xE06CFC845 846#define mmTPC0_CFG_QM_SRF_28 0xE06D00847 848#define mmTPC0_CFG_QM_SRF_29 0xE06D04849 850#define mmTPC0_CFG_QM_SRF_30 0xE06D08851 852#define mmTPC0_CFG_QM_SRF_31 0xE06D0C853 854#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06D10855 856#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D14857 858#define mmTPC0_CFG_ARUSER 0xE06D18859 860#define mmTPC0_CFG_AWUSER 0xE06D1C861 862#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE06E00863 864#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE06E04865 866#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE06E08867 868#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE06E0C869 870#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE06E10871 872#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE06E14873 874#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE06E18875 876#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE06E1C877 878#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE06E20879 880#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE06E24881 882#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE06E28883 884#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE06E2C885 886#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */887