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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_CMDQ_REGS_H_14#define ASIC_REG_TPC0_CMDQ_REGS_H_15 16/*17 *****************************************18 * TPC0_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22#define mmTPC0_CMDQ_GLBL_CFG0 0xE0900023 24#define mmTPC0_CMDQ_GLBL_CFG1 0xE0900425 26#define mmTPC0_CMDQ_GLBL_PROT 0xE0900827 28#define mmTPC0_CMDQ_GLBL_ERR_CFG 0xE0900C29 30#define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO 0xE0901031 32#define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI 0xE0901433 34#define mmTPC0_CMDQ_GLBL_ERR_WDATA 0xE0901835 36#define mmTPC0_CMDQ_GLBL_SECURE_PROPS 0xE0901C37 38#define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS 0xE0902039 40#define mmTPC0_CMDQ_GLBL_STS0 0xE0902441 42#define mmTPC0_CMDQ_GLBL_STS1 0xE0902843 44#define mmTPC0_CMDQ_CQ_CFG0 0xE090B045 46#define mmTPC0_CMDQ_CQ_CFG1 0xE090B447 48#define mmTPC0_CMDQ_CQ_ARUSER 0xE090B849 50#define mmTPC0_CMDQ_CQ_PTR_LO 0xE090C051 52#define mmTPC0_CMDQ_CQ_PTR_HI 0xE090C453 54#define mmTPC0_CMDQ_CQ_TSIZE 0xE090C855 56#define mmTPC0_CMDQ_CQ_CTL 0xE090CC57 58#define mmTPC0_CMDQ_CQ_PTR_LO_STS 0xE090D459 60#define mmTPC0_CMDQ_CQ_PTR_HI_STS 0xE090D861 62#define mmTPC0_CMDQ_CQ_TSIZE_STS 0xE090DC63 64#define mmTPC0_CMDQ_CQ_CTL_STS 0xE090E065 66#define mmTPC0_CMDQ_CQ_STS0 0xE090E467 68#define mmTPC0_CMDQ_CQ_STS1 0xE090E869 70#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN 0xE090F071 72#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE090F473 74#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT 0xE090F875 76#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE090FC77 78#define mmTPC0_CMDQ_CQ_IFIFO_CNT 0xE0910879 80#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE0912081 82#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE0912483 84#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE0912885 86#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE0912C87 88#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE0913089 90#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE0913491 92#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE0913893 94#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE0913C95 96#define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE0914097 98#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE0914499 100#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE09148101 102#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE0914C103 104#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE09150105 106#define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE09154107 108#define mmTPC0_CMDQ_CP_FENCE0_RDATA 0xE09158109 110#define mmTPC0_CMDQ_CP_FENCE1_RDATA 0xE0915C111 112#define mmTPC0_CMDQ_CP_FENCE2_RDATA 0xE09160113 114#define mmTPC0_CMDQ_CP_FENCE3_RDATA 0xE09164115 116#define mmTPC0_CMDQ_CP_FENCE0_CNT 0xE09168117 118#define mmTPC0_CMDQ_CP_FENCE1_CNT 0xE0916C119 120#define mmTPC0_CMDQ_CP_FENCE2_CNT 0xE09170121 122#define mmTPC0_CMDQ_CP_FENCE3_CNT 0xE09174123 124#define mmTPC0_CMDQ_CP_STS 0xE09178125 126#define mmTPC0_CMDQ_CP_CURRENT_INST_LO 0xE0917C127 128#define mmTPC0_CMDQ_CP_CURRENT_INST_HI 0xE09180129 130#define mmTPC0_CMDQ_CP_BARRIER_CFG 0xE09184131 132#define mmTPC0_CMDQ_CP_DBG_0 0xE09188133 134#define mmTPC0_CMDQ_CQ_BUF_ADDR 0xE09308135 136#define mmTPC0_CMDQ_CQ_BUF_RDATA 0xE0930C137 138#endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */139