209 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_NRTR_MASKS_H_14#define ASIC_REG_TPC0_NRTR_MASKS_H_15 16/*17 *****************************************18 * TPC0_NRTR (Prototype: IF_NRTR)19 *****************************************20 */21 22/* TPC0_NRTR_HBW_MAX_CRED */23#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 024#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F25#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 826#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F0027#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 1628#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F000029#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 2430#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F00000031 32/* TPC0_NRTR_LBW_MAX_CRED */33#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 034#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F35#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 836#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F0037#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 1638#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F000039#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 2440#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F00000041 42/* TPC0_NRTR_DBG_E_ARB */43#define TPC0_NRTR_DBG_E_ARB_W_SHIFT 044#define TPC0_NRTR_DBG_E_ARB_W_MASK 0x745#define TPC0_NRTR_DBG_E_ARB_S_SHIFT 846#define TPC0_NRTR_DBG_E_ARB_S_MASK 0x70047#define TPC0_NRTR_DBG_E_ARB_N_SHIFT 1648#define TPC0_NRTR_DBG_E_ARB_N_MASK 0x7000049#define TPC0_NRTR_DBG_E_ARB_L_SHIFT 2450#define TPC0_NRTR_DBG_E_ARB_L_MASK 0x700000051 52/* TPC0_NRTR_DBG_W_ARB */53#define TPC0_NRTR_DBG_W_ARB_E_SHIFT 054#define TPC0_NRTR_DBG_W_ARB_E_MASK 0x755#define TPC0_NRTR_DBG_W_ARB_S_SHIFT 856#define TPC0_NRTR_DBG_W_ARB_S_MASK 0x70057#define TPC0_NRTR_DBG_W_ARB_N_SHIFT 1658#define TPC0_NRTR_DBG_W_ARB_N_MASK 0x7000059#define TPC0_NRTR_DBG_W_ARB_L_SHIFT 2460#define TPC0_NRTR_DBG_W_ARB_L_MASK 0x700000061 62/* TPC0_NRTR_DBG_N_ARB */63#define TPC0_NRTR_DBG_N_ARB_W_SHIFT 064#define TPC0_NRTR_DBG_N_ARB_W_MASK 0x765#define TPC0_NRTR_DBG_N_ARB_E_SHIFT 866#define TPC0_NRTR_DBG_N_ARB_E_MASK 0x70067#define TPC0_NRTR_DBG_N_ARB_S_SHIFT 1668#define TPC0_NRTR_DBG_N_ARB_S_MASK 0x7000069#define TPC0_NRTR_DBG_N_ARB_L_SHIFT 2470#define TPC0_NRTR_DBG_N_ARB_L_MASK 0x700000071 72/* TPC0_NRTR_DBG_S_ARB */73#define TPC0_NRTR_DBG_S_ARB_W_SHIFT 074#define TPC0_NRTR_DBG_S_ARB_W_MASK 0x775#define TPC0_NRTR_DBG_S_ARB_E_SHIFT 876#define TPC0_NRTR_DBG_S_ARB_E_MASK 0x70077#define TPC0_NRTR_DBG_S_ARB_N_SHIFT 1678#define TPC0_NRTR_DBG_S_ARB_N_MASK 0x7000079#define TPC0_NRTR_DBG_S_ARB_L_SHIFT 2480#define TPC0_NRTR_DBG_S_ARB_L_MASK 0x700000081 82/* TPC0_NRTR_DBG_L_ARB */83#define TPC0_NRTR_DBG_L_ARB_W_SHIFT 084#define TPC0_NRTR_DBG_L_ARB_W_MASK 0x785#define TPC0_NRTR_DBG_L_ARB_E_SHIFT 886#define TPC0_NRTR_DBG_L_ARB_E_MASK 0x70087#define TPC0_NRTR_DBG_L_ARB_S_SHIFT 1688#define TPC0_NRTR_DBG_L_ARB_S_MASK 0x7000089#define TPC0_NRTR_DBG_L_ARB_N_SHIFT 2490#define TPC0_NRTR_DBG_L_ARB_N_MASK 0x700000091 92/* TPC0_NRTR_DBG_E_ARB_MAX */93#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 094#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F95 96/* TPC0_NRTR_DBG_W_ARB_MAX */97#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 098#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F99 100/* TPC0_NRTR_DBG_N_ARB_MAX */101#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0102#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F103 104/* TPC0_NRTR_DBG_S_ARB_MAX */105#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0106#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F107 108/* TPC0_NRTR_DBG_L_ARB_MAX */109#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0110#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F111 112/* TPC0_NRTR_SPLIT_COEF */113#define TPC0_NRTR_SPLIT_COEF_VAL_SHIFT 0114#define TPC0_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF115 116/* TPC0_NRTR_SPLIT_CFG */117#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0118#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1119#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1120#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2121#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2122#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC123#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4124#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10125#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5126#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20127#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6128#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0129 130/* TPC0_NRTR_SPLIT_RD_SAT */131#define TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0132#define TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF133 134/* TPC0_NRTR_SPLIT_RD_RST_TOKEN */135#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0136#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF137 138/* TPC0_NRTR_SPLIT_RD_TIMEOUT */139#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0140#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF141 142/* TPC0_NRTR_SPLIT_WR_SAT */143#define TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0144#define TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF145 146/* TPC0_NRTR_WPLIT_WR_TST_TOLEN */147#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0148#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF149 150/* TPC0_NRTR_SPLIT_WR_TIMEOUT */151#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0152#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF153 154/* TPC0_NRTR_HBW_RANGE_HIT */155#define TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT 0156#define TPC0_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF157 158/* TPC0_NRTR_HBW_RANGE_MASK_L */159#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0160#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF161 162/* TPC0_NRTR_HBW_RANGE_MASK_H */163#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0164#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF165 166/* TPC0_NRTR_HBW_RANGE_BASE_L */167#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0168#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF169 170/* TPC0_NRTR_HBW_RANGE_BASE_H */171#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0172#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF173 174/* TPC0_NRTR_LBW_RANGE_HIT */175#define TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT 0176#define TPC0_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF177 178/* TPC0_NRTR_LBW_RANGE_MASK */179#define TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0180#define TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF181 182/* TPC0_NRTR_LBW_RANGE_BASE */183#define TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0184#define TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF185 186/* TPC0_NRTR_RGLTR */187#define TPC0_NRTR_RGLTR_WR_EN_SHIFT 0188#define TPC0_NRTR_RGLTR_WR_EN_MASK 0x1189#define TPC0_NRTR_RGLTR_RD_EN_SHIFT 4190#define TPC0_NRTR_RGLTR_RD_EN_MASK 0x10191 192/* TPC0_NRTR_RGLTR_WR_RESULT */193#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0194#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF195 196/* TPC0_NRTR_RGLTR_RD_RESULT */197#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0198#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF199 200/* TPC0_NRTR_SCRAMB_EN */201#define TPC0_NRTR_SCRAMB_EN_VAL_SHIFT 0202#define TPC0_NRTR_SCRAMB_EN_VAL_MASK 0x1203 204/* TPC0_NRTR_NON_LIN_SCRAMB */205#define TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0206#define TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1207 208#endif /* ASIC_REG_TPC0_NRTR_MASKS_H_ */209