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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_QM_MASKS_H_14#define ASIC_REG_TPC0_QM_MASKS_H_15 16/*17 *****************************************18 * TPC0_QM (Prototype: QMAN)19 *****************************************20 */21 22/* TPC0_QM_GLBL_CFG0 */23#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 024#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x125#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 126#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x227#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 228#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x429#define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 330#define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x831 32/* TPC0_QM_GLBL_CFG1 */33#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 034#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x135#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 136#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x237#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 238#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x439#define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 340#define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x841#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 842#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x10043#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 944#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x20045#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 1046#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x40047#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 1148#define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x80049 50/* TPC0_QM_GLBL_PROT */51#define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 052#define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x153#define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 154#define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x255#define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 256#define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x457#define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 358#define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x859#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 460#define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x1061#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 562#define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x2063#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 664#define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x4065#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 766#define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x8067 68/* TPC0_QM_GLBL_ERR_CFG */69#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 070#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x171#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 172#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x273#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 274#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x475#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 376#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x877#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 478#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1079#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 580#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x2081#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 682#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x4083#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 784#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x8085#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 886#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x10087#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 988#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x20089#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 1090#define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x40091#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 1192#define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x80093 94/* TPC0_QM_GLBL_ERR_ADDR_LO */95#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 096#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF97 98/* TPC0_QM_GLBL_ERR_ADDR_HI */99#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0100#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF101 102/* TPC0_QM_GLBL_ERR_WDATA */103#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0104#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF105 106/* TPC0_QM_GLBL_SECURE_PROPS */107#define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0108#define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF109#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10110#define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400111 112/* TPC0_QM_GLBL_NON_SECURE_PROPS */113#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0114#define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF115#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10116#define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400117 118/* TPC0_QM_GLBL_STS0 */119#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0120#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1121#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1122#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2123#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2124#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4125#define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3126#define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8127#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4128#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10129#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5130#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20131#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6132#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40133#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7134#define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80135 136/* TPC0_QM_GLBL_STS1 */137#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0138#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1139#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1140#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2141#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2142#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4143#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3144#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8145#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4146#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10147#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5148#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20149#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8150#define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100151#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9152#define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200153#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10154#define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400155#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11156#define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800157 158/* TPC0_QM_PQ_BASE_LO */159#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0160#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF161 162/* TPC0_QM_PQ_BASE_HI */163#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0164#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF165 166/* TPC0_QM_PQ_SIZE */167#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0168#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF169 170/* TPC0_QM_PQ_PI */171#define TPC0_QM_PQ_PI_VAL_SHIFT 0172#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF173 174/* TPC0_QM_PQ_CI */175#define TPC0_QM_PQ_CI_VAL_SHIFT 0176#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF177 178/* TPC0_QM_PQ_CFG0 */179#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0180#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1181 182/* TPC0_QM_PQ_CFG1 */183#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0184#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF185#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16186#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000187 188/* TPC0_QM_PQ_ARUSER */189#define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0190#define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1191#define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1192#define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2193 194/* TPC0_QM_PQ_PUSH0 */195#define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0196#define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF197 198/* TPC0_QM_PQ_PUSH1 */199#define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0200#define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF201 202/* TPC0_QM_PQ_PUSH2 */203#define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0204#define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF205 206/* TPC0_QM_PQ_PUSH3 */207#define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0208#define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF209#define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16210#define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000211 212/* TPC0_QM_PQ_STS0 */213#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0214#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF215#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16216#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000217 218/* TPC0_QM_PQ_STS1 */219#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0220#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF221#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30222#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000223#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31224#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000225 226/* TPC0_QM_PQ_RD_RATE_LIM_EN */227#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0228#define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1229 230/* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */231#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0232#define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF233 234/* TPC0_QM_PQ_RD_RATE_LIM_SAT */235#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0236#define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF237 238/* TPC0_QM_PQ_RD_RATE_LIM_TOUT */239#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0240#define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF241 242/* TPC0_QM_CQ_CFG0 */243#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0244#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1245 246/* TPC0_QM_CQ_CFG1 */247#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0248#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF249#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16250#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000251 252/* TPC0_QM_CQ_ARUSER */253#define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0254#define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1255#define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1256#define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2257 258/* TPC0_QM_CQ_PTR_LO */259#define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0260#define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF261 262/* TPC0_QM_CQ_PTR_HI */263#define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0264#define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF265 266/* TPC0_QM_CQ_TSIZE */267#define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0268#define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF269 270/* TPC0_QM_CQ_CTL */271#define TPC0_QM_CQ_CTL_RPT_SHIFT 0272#define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF273#define TPC0_QM_CQ_CTL_CTL_SHIFT 16274#define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000275 276/* TPC0_QM_CQ_PTR_LO_STS */277#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0278#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF279 280/* TPC0_QM_CQ_PTR_HI_STS */281#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0282#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF283 284/* TPC0_QM_CQ_TSIZE_STS */285#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0286#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF287 288/* TPC0_QM_CQ_CTL_STS */289#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0290#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF291#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16292#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000293 294/* TPC0_QM_CQ_STS0 */295#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0296#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF297#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16298#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000299 300/* TPC0_QM_CQ_STS1 */301#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0302#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF303#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30304#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000305#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31306#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000307 308/* TPC0_QM_CQ_RD_RATE_LIM_EN */309#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0310#define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1311 312/* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */313#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0314#define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF315 316/* TPC0_QM_CQ_RD_RATE_LIM_SAT */317#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0318#define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF319 320/* TPC0_QM_CQ_RD_RATE_LIM_TOUT */321#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0322#define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF323 324/* TPC0_QM_CQ_IFIFO_CNT */325#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0326#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3327 328/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */329#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0330#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF331 332/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */333#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0334#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF335 336/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */337#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0338#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF339 340/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */341#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0342#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF343 344/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */345#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0346#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF347 348/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */349#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0350#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF351 352/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */353#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0354#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF355 356/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */357#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0358#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF359 360/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */361#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0362#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF363 364/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */365#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0366#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF367 368/* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */369#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0370#define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF371 372/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */373#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0374#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF375 376/* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */377#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0378#define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF379 380/* TPC0_QM_CP_LDMA_COMMIT_OFFSET */381#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0382#define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF383 384/* TPC0_QM_CP_FENCE0_RDATA */385#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0386#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF387 388/* TPC0_QM_CP_FENCE1_RDATA */389#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0390#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF391 392/* TPC0_QM_CP_FENCE2_RDATA */393#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0394#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF395 396/* TPC0_QM_CP_FENCE3_RDATA */397#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0398#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF399 400/* TPC0_QM_CP_FENCE0_CNT */401#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0402#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF403 404/* TPC0_QM_CP_FENCE1_CNT */405#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0406#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF407 408/* TPC0_QM_CP_FENCE2_CNT */409#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0410#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF411 412/* TPC0_QM_CP_FENCE3_CNT */413#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0414#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF415 416/* TPC0_QM_CP_STS */417#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0418#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF419#define TPC0_QM_CP_STS_ERDY_SHIFT 16420#define TPC0_QM_CP_STS_ERDY_MASK 0x10000421#define TPC0_QM_CP_STS_RRDY_SHIFT 17422#define TPC0_QM_CP_STS_RRDY_MASK 0x20000423#define TPC0_QM_CP_STS_MRDY_SHIFT 18424#define TPC0_QM_CP_STS_MRDY_MASK 0x40000425#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19426#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000427#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20428#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000429#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22430#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000431 432/* TPC0_QM_CP_CURRENT_INST_LO */433#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0434#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF435 436/* TPC0_QM_CP_CURRENT_INST_HI */437#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0438#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF439 440/* TPC0_QM_CP_BARRIER_CFG */441#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0442#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF443 444/* TPC0_QM_CP_DBG_0 */445#define TPC0_QM_CP_DBG_0_VAL_SHIFT 0446#define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF447 448/* TPC0_QM_PQ_BUF_ADDR */449#define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0450#define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF451 452/* TPC0_QM_PQ_BUF_RDATA */453#define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0454#define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF455 456/* TPC0_QM_CQ_BUF_ADDR */457#define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0458#define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF459 460/* TPC0_QM_CQ_BUF_RDATA */461#define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0462#define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF463 464#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */465