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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 **       DO NOT EDIT BELOW        **11 ************************************/12 13#ifndef ASIC_REG_TPC0_QM_REGS_H_14#define ASIC_REG_TPC0_QM_REGS_H_15 16/*17 *****************************************18 *   TPC0_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmTPC0_QM_GLBL_CFG0                                          0xE0800023 24#define mmTPC0_QM_GLBL_CFG1                                          0xE0800425 26#define mmTPC0_QM_GLBL_PROT                                          0xE0800827 28#define mmTPC0_QM_GLBL_ERR_CFG                                       0xE0800C29 30#define mmTPC0_QM_GLBL_ERR_ADDR_LO                                   0xE0801031 32#define mmTPC0_QM_GLBL_ERR_ADDR_HI                                   0xE0801433 34#define mmTPC0_QM_GLBL_ERR_WDATA                                     0xE0801835 36#define mmTPC0_QM_GLBL_SECURE_PROPS                                  0xE0801C37 38#define mmTPC0_QM_GLBL_NON_SECURE_PROPS                              0xE0802039 40#define mmTPC0_QM_GLBL_STS0                                          0xE0802441 42#define mmTPC0_QM_GLBL_STS1                                          0xE0802843 44#define mmTPC0_QM_PQ_BASE_LO                                         0xE0806045 46#define mmTPC0_QM_PQ_BASE_HI                                         0xE0806447 48#define mmTPC0_QM_PQ_SIZE                                            0xE0806849 50#define mmTPC0_QM_PQ_PI                                              0xE0806C51 52#define mmTPC0_QM_PQ_CI                                              0xE0807053 54#define mmTPC0_QM_PQ_CFG0                                            0xE0807455 56#define mmTPC0_QM_PQ_CFG1                                            0xE0807857 58#define mmTPC0_QM_PQ_ARUSER                                          0xE0807C59 60#define mmTPC0_QM_PQ_PUSH0                                           0xE0808061 62#define mmTPC0_QM_PQ_PUSH1                                           0xE0808463 64#define mmTPC0_QM_PQ_PUSH2                                           0xE0808865 66#define mmTPC0_QM_PQ_PUSH3                                           0xE0808C67 68#define mmTPC0_QM_PQ_STS0                                            0xE0809069 70#define mmTPC0_QM_PQ_STS1                                            0xE0809471 72#define mmTPC0_QM_PQ_RD_RATE_LIM_EN                                  0xE080A073 74#define mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN                           0xE080A475 76#define mmTPC0_QM_PQ_RD_RATE_LIM_SAT                                 0xE080A877 78#define mmTPC0_QM_PQ_RD_RATE_LIM_TOUT                                0xE080AC79 80#define mmTPC0_QM_CQ_CFG0                                            0xE080B081 82#define mmTPC0_QM_CQ_CFG1                                            0xE080B483 84#define mmTPC0_QM_CQ_ARUSER                                          0xE080B885 86#define mmTPC0_QM_CQ_PTR_LO                                          0xE080C087 88#define mmTPC0_QM_CQ_PTR_HI                                          0xE080C489 90#define mmTPC0_QM_CQ_TSIZE                                           0xE080C891 92#define mmTPC0_QM_CQ_CTL                                             0xE080CC93 94#define mmTPC0_QM_CQ_PTR_LO_STS                                      0xE080D495 96#define mmTPC0_QM_CQ_PTR_HI_STS                                      0xE080D897 98#define mmTPC0_QM_CQ_TSIZE_STS                                       0xE080DC99 100#define mmTPC0_QM_CQ_CTL_STS                                         0xE080E0101 102#define mmTPC0_QM_CQ_STS0                                            0xE080E4103 104#define mmTPC0_QM_CQ_STS1                                            0xE080E8105 106#define mmTPC0_QM_CQ_RD_RATE_LIM_EN                                  0xE080F0107 108#define mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN                           0xE080F4109 110#define mmTPC0_QM_CQ_RD_RATE_LIM_SAT                                 0xE080F8111 112#define mmTPC0_QM_CQ_RD_RATE_LIM_TOUT                                0xE080FC113 114#define mmTPC0_QM_CQ_IFIFO_CNT                                       0xE08108115 116#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO                               0xE08120117 118#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI                               0xE08124119 120#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO                               0xE08128121 122#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI                               0xE0812C123 124#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO                               0xE08130125 126#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI                               0xE08134127 128#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO                               0xE08138129 130#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI                               0xE0813C131 132#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET                               0xE08140133 134#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET                         0xE08144135 136#define mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET                         0xE08148137 138#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET                         0xE0814C139 140#define mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET                         0xE08150141 142#define mmTPC0_QM_CP_LDMA_COMMIT_OFFSET                              0xE08154143 144#define mmTPC0_QM_CP_FENCE0_RDATA                                    0xE08158145 146#define mmTPC0_QM_CP_FENCE1_RDATA                                    0xE0815C147 148#define mmTPC0_QM_CP_FENCE2_RDATA                                    0xE08160149 150#define mmTPC0_QM_CP_FENCE3_RDATA                                    0xE08164151 152#define mmTPC0_QM_CP_FENCE0_CNT                                      0xE08168153 154#define mmTPC0_QM_CP_FENCE1_CNT                                      0xE0816C155 156#define mmTPC0_QM_CP_FENCE2_CNT                                      0xE08170157 158#define mmTPC0_QM_CP_FENCE3_CNT                                      0xE08174159 160#define mmTPC0_QM_CP_STS                                             0xE08178161 162#define mmTPC0_QM_CP_CURRENT_INST_LO                                 0xE0817C163 164#define mmTPC0_QM_CP_CURRENT_INST_HI                                 0xE08180165 166#define mmTPC0_QM_CP_BARRIER_CFG                                     0xE08184167 168#define mmTPC0_QM_CP_DBG_0                                           0xE08188169 170#define mmTPC0_QM_PQ_BUF_ADDR                                        0xE08300171 172#define mmTPC0_QM_PQ_BUF_RDATA                                       0xE08304173 174#define mmTPC0_QM_CQ_BUF_ADDR                                        0xE08308175 176#define mmTPC0_QM_CQ_BUF_RDATA                                       0xE0830C177 178#endif /* ASIC_REG_TPC0_QM_REGS_H_ */179