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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC1_CFG_REGS_H_14#define ASIC_REG_TPC1_CFG_REGS_H_15 16/*17 *****************************************18 * TPC1_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE4640023 24#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE4640425 26#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE4640827 28#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C29 30#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE4641031 32#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE4641433 34#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE4641835 36#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE4641C37 38#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4642039 40#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE4642441 42#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE4642843 44#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE4642C45 46#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE4643047 48#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE4643449 50#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4643851 52#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE4643C53 54#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE4644055 56#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE4644457 58#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE4644859 60#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE4644C61 62#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4645063 64#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE4645465 66#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE4645867 68#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE4645C69 70#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4646071 72#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE4646473 74#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE4646875 76#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE4646C77 78#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE4647079 80#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE4647481 82#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4647883 84#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE4647C85 86#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE4648087 88#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE4648489 90#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE4648891 92#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE4648C93 94#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4649095 96#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE4649497 98#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE4649899 100#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE4649C101 102#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE464A0103 104#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE464A4105 106#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE464A8107 108#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE464AC109 110#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE464B0111 112#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE464B4113 114#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE464B8115 116#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE464BC117 118#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE464C0119 120#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE464C4121 122#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE464C8123 124#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE464CC125 126#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE464D0127 128#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE464D4129 130#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464D8131 132#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464DC133 134#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE464E0135 136#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464E4137 138#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464E8139 140#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464EC141 142#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464F0143 144#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464F4145 146#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464F8147 148#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE464FC149 150#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE46500151 152#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE46504153 154#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE46508155 156#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE4650C157 158#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE46510159 160#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE46514161 162#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE46518163 164#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE4651C165 166#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE46520167 168#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE46524169 170#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE46528171 172#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE4652C173 174#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE46530175 176#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE46534177 178#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE46538179 180#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE4653C181 182#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE46540183 184#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE46544185 186#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE46548187 188#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE4654C189 190#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE46550191 192#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE46554193 194#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46558195 196#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE4655C197 198#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE46560199 200#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46564201 202#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE46568203 204#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE4656C205 206#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46570207 208#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46574209 210#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE46578211 212#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE4657C213 214#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE46580215 216#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46584217 218#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46588219 220#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE4658C221 222#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE46590223 224#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE46594225 226#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46598227 228#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE4659C229 230#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE465A0231 232#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE465A4233 234#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE465A8235 236#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE465AC237 238#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE465B0239 240#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE465B4241 242#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE465B8243 244#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE465BC245 246#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE465C0247 248#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE465C4249 250#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE465C8251 252#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE465CC253 254#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE465D0255 256#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE465D4257 258#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE465D8259 260#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE465DC261 262#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE465E0263 264#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE465E4265 266#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE465E8267 268#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE465EC269 270#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE465F0271 272#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE465F4273 274#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE465F8275 276#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE465FC277 278#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE46600279 280#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE46604281 282#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46608283 284#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE4660C285 286#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE46610287 288#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46614289 290#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE46618291 292#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE4661C293 294#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46620295 296#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46624297 298#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE46628299 300#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE4662C301 302#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE46630303 304#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE46634305 306#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE46638307 308#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE4663C309 310#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE46640311 312#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE46644313 314#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE46648315 316#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE4664C317 318#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE46650319 320#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE46654321 322#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE46658323 324#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE4665C325 326#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46660327 328#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE46664329 330#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46668331 332#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE4666C333 334#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46670335 336#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE46674337 338#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE46678339 340#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE4667C341 342#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE46680343 344#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE46684345 346#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE46688347 348#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE4668C349 350#define mmTPC1_CFG_KERNEL_SRF_0 0xE46690351 352#define mmTPC1_CFG_KERNEL_SRF_1 0xE46694353 354#define mmTPC1_CFG_KERNEL_SRF_2 0xE46698355 356#define mmTPC1_CFG_KERNEL_SRF_3 0xE4669C357 358#define mmTPC1_CFG_KERNEL_SRF_4 0xE466A0359 360#define mmTPC1_CFG_KERNEL_SRF_5 0xE466A4361 362#define mmTPC1_CFG_KERNEL_SRF_6 0xE466A8363 364#define mmTPC1_CFG_KERNEL_SRF_7 0xE466AC365 366#define mmTPC1_CFG_KERNEL_SRF_8 0xE466B0367 368#define mmTPC1_CFG_KERNEL_SRF_9 0xE466B4369 370#define mmTPC1_CFG_KERNEL_SRF_10 0xE466B8371 372#define mmTPC1_CFG_KERNEL_SRF_11 0xE466BC373 374#define mmTPC1_CFG_KERNEL_SRF_12 0xE466C0375 376#define mmTPC1_CFG_KERNEL_SRF_13 0xE466C4377 378#define mmTPC1_CFG_KERNEL_SRF_14 0xE466C8379 380#define mmTPC1_CFG_KERNEL_SRF_15 0xE466CC381 382#define mmTPC1_CFG_KERNEL_SRF_16 0xE466D0383 384#define mmTPC1_CFG_KERNEL_SRF_17 0xE466D4385 386#define mmTPC1_CFG_KERNEL_SRF_18 0xE466D8387 388#define mmTPC1_CFG_KERNEL_SRF_19 0xE466DC389 390#define mmTPC1_CFG_KERNEL_SRF_20 0xE466E0391 392#define mmTPC1_CFG_KERNEL_SRF_21 0xE466E4393 394#define mmTPC1_CFG_KERNEL_SRF_22 0xE466E8395 396#define mmTPC1_CFG_KERNEL_SRF_23 0xE466EC397 398#define mmTPC1_CFG_KERNEL_SRF_24 0xE466F0399 400#define mmTPC1_CFG_KERNEL_SRF_25 0xE466F4401 402#define mmTPC1_CFG_KERNEL_SRF_26 0xE466F8403 404#define mmTPC1_CFG_KERNEL_SRF_27 0xE466FC405 406#define mmTPC1_CFG_KERNEL_SRF_28 0xE46700407 408#define mmTPC1_CFG_KERNEL_SRF_29 0xE46704409 410#define mmTPC1_CFG_KERNEL_SRF_30 0xE46708411 412#define mmTPC1_CFG_KERNEL_SRF_31 0xE4670C413 414#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE46710415 416#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46714417 418#define mmTPC1_CFG_RESERVED_DESC_END 0xE46738419 420#define mmTPC1_CFG_ROUND_CSR 0xE467FC421 422#define mmTPC1_CFG_TBUF_BASE_ADDR_LOW 0xE46800423 424#define mmTPC1_CFG_TBUF_BASE_ADDR_HIGH 0xE46804425 426#define mmTPC1_CFG_SEMAPHORE 0xE46808427 428#define mmTPC1_CFG_VFLAGS 0xE4680C429 430#define mmTPC1_CFG_SFLAGS 0xE46810431 432#define mmTPC1_CFG_LFSR_POLYNOM 0xE46818433 434#define mmTPC1_CFG_STATUS 0xE4681C435 436#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46820437 438#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46824439 440#define mmTPC1_CFG_SM_BASE_ADDRESS_LOW 0xE46828441 442#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4682C443 444#define mmTPC1_CFG_TPC_CMD 0xE46830445 446#define mmTPC1_CFG_TPC_EXECUTE 0xE46838447 448#define mmTPC1_CFG_TPC_STALL 0xE4683C449 450#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46840451 452#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46844453 454#define mmTPC1_CFG_MSS_CONFIG 0xE46854455 456#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46858457 458#define mmTPC1_CFG_TPC_INTR_MASK 0xE4685C459 460#define mmTPC1_CFG_TSB_CONFIG 0xE46860461 462#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00463 464#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04465 466#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08467 468#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C469 470#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10471 472#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14473 474#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE46A18475 476#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A1C477 478#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A20479 480#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE46A24481 482#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A28483 484#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A2C485 486#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE46A30487 488#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A34489 490#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A38491 492#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE46A3C493 494#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A40495 496#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A44497 498#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE46A48499 500#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A4C501 502#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A50503 504#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A54505 506#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A58507 508#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A5C509 510#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A60511 512#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE46A64513 514#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A68515 516#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A6C517 518#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE46A70519 520#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A74521 522#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A78523 524#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE46A7C525 526#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A80527 528#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A84529 530#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE46A88531 532#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A8C533 534#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A90535 536#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE46A94537 538#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A98539 540#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A9C541 542#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46AA0543 544#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46AA4545 546#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46AA8547 548#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46AAC549 550#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE46AB0551 552#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46AB4553 554#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46AB8555 556#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE46ABC557 558#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46AC0559 560#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46AC4561 562#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE46AC8563 564#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46ACC565 566#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46AD0567 568#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE46AD4569 570#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AD8571 572#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46ADC573 574#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE46AE0575 576#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AE4577 578#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AE8579 580#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AEC581 582#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AF0583 584#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AF4585 586#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46AF8587 588#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE46AFC589 590#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46B00591 592#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46B04593 594#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE46B08595 596#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46B0C597 598#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46B10599 600#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE46B14601 602#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46B18603 604#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46B1C605 606#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE46B20607 608#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46B24609 610#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46B28611 612#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE46B2C613 614#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46B30615 616#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46B34617 618#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46B38619 620#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46B3C621 622#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46B40623 624#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46B44625 626#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE46B48627 628#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46B4C629 630#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46B50631 632#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE46B54633 634#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B58635 636#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B5C637 638#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE46B60639 640#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B64641 642#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B68643 644#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE46B6C645 646#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B70647 648#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B74649 650#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE46B78651 652#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B7C653 654#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B80655 656#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B84657 658#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B88659 660#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B8C661 662#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B90663 664#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE46B94665 666#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B98667 668#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B9C669 670#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE46BA0671 672#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46BA4673 674#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46BA8675 676#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE46BAC677 678#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46BB0679 680#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46BB4681 682#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE46BB8683 684#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46BBC685 686#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46BC0687 688#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE46BC4689 690#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46BC8691 692#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46BCC693 694#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46BD0695 696#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46BD4697 698#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46BD8699 700#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46BDC701 702#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE46BE0703 704#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46BE4705 706#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46BE8707 708#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE46BEC709 710#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46BF0711 712#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46BF4713 714#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE46BF8715 716#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46BFC717 718#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46C00719 720#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE46C04721 722#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46C08723 724#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46C0C725 726#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE46C10727 728#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46C14729 730#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46C18731 732#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46C1C733 734#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46C20735 736#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46C24737 738#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46C28739 740#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE46C2C741 742#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46C30743 744#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46C34745 746#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE46C38747 748#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46C3C749 750#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46C40751 752#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE46C44753 754#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46C48755 756#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46C4C757 758#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE46C50759 760#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46C54761 762#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46C58763 764#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE46C5C765 766#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46C60767 768#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46C64769 770#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46C68771 772#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46C6C773 774#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46C70775 776#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46C74777 778#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46C78779 780#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46C7C781 782#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46C80783 784#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46C84785 786#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46C88787 788#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46C8C789 790#define mmTPC1_CFG_QM_SRF_0 0xE46C90791 792#define mmTPC1_CFG_QM_SRF_1 0xE46C94793 794#define mmTPC1_CFG_QM_SRF_2 0xE46C98795 796#define mmTPC1_CFG_QM_SRF_3 0xE46C9C797 798#define mmTPC1_CFG_QM_SRF_4 0xE46CA0799 800#define mmTPC1_CFG_QM_SRF_5 0xE46CA4801 802#define mmTPC1_CFG_QM_SRF_6 0xE46CA8803 804#define mmTPC1_CFG_QM_SRF_7 0xE46CAC805 806#define mmTPC1_CFG_QM_SRF_8 0xE46CB0807 808#define mmTPC1_CFG_QM_SRF_9 0xE46CB4809 810#define mmTPC1_CFG_QM_SRF_10 0xE46CB8811 812#define mmTPC1_CFG_QM_SRF_11 0xE46CBC813 814#define mmTPC1_CFG_QM_SRF_12 0xE46CC0815 816#define mmTPC1_CFG_QM_SRF_13 0xE46CC4817 818#define mmTPC1_CFG_QM_SRF_14 0xE46CC8819 820#define mmTPC1_CFG_QM_SRF_15 0xE46CCC821 822#define mmTPC1_CFG_QM_SRF_16 0xE46CD0823 824#define mmTPC1_CFG_QM_SRF_17 0xE46CD4825 826#define mmTPC1_CFG_QM_SRF_18 0xE46CD8827 828#define mmTPC1_CFG_QM_SRF_19 0xE46CDC829 830#define mmTPC1_CFG_QM_SRF_20 0xE46CE0831 832#define mmTPC1_CFG_QM_SRF_21 0xE46CE4833 834#define mmTPC1_CFG_QM_SRF_22 0xE46CE8835 836#define mmTPC1_CFG_QM_SRF_23 0xE46CEC837 838#define mmTPC1_CFG_QM_SRF_24 0xE46CF0839 840#define mmTPC1_CFG_QM_SRF_25 0xE46CF4841 842#define mmTPC1_CFG_QM_SRF_26 0xE46CF8843 844#define mmTPC1_CFG_QM_SRF_27 0xE46CFC845 846#define mmTPC1_CFG_QM_SRF_28 0xE46D00847 848#define mmTPC1_CFG_QM_SRF_29 0xE46D04849 850#define mmTPC1_CFG_QM_SRF_30 0xE46D08851 852#define mmTPC1_CFG_QM_SRF_31 0xE46D0C853 854#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46D10855 856#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D14857 858#define mmTPC1_CFG_ARUSER 0xE46D18859 860#define mmTPC1_CFG_AWUSER 0xE46D1C861 862#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE46E00863 864#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE46E04865 866#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE46E08867 868#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE46E0C869 870#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE46E10871 872#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE46E14873 874#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE46E18875 876#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE46E1C877 878#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE46E20879 880#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE46E24881 882#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE46E28883 884#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE46E2C885 886#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */887