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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC2_CFG_REGS_H_14#define ASIC_REG_TPC2_CFG_REGS_H_15 16/*17 *****************************************18 * TPC2_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE8640023 24#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE8640425 26#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE8640827 28#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C29 30#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE8641031 32#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE8641433 34#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE8641835 36#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641C37 38#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8642039 40#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE8642441 42#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE8642843 44#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642C45 46#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE8643047 48#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE8643449 50#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8643851 52#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE8643C53 54#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE8644055 56#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE8644457 58#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE8644859 60#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8644C61 62#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8645063 64#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE8645465 66#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE8645867 68#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8645C69 70#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8646071 72#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE8646473 74#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE8646875 76#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8646C77 78#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE8647079 80#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE8647481 82#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8647883 84#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE8647C85 86#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE8648087 88#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE8648489 90#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE8648891 92#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8648C93 94#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8649095 96#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE8649497 98#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE8649899 100#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8649C101 102#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE864A0103 104#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE864A4105 106#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE864A8107 108#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE864AC109 110#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE864B0111 112#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE864B4113 114#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE864B8115 116#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE864BC117 118#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE864C0119 120#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE864C4121 122#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE864C8123 124#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE864CC125 126#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE864D0127 128#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE864D4129 130#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864D8131 132#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864DC133 134#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE864E0135 136#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864E4137 138#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864E8139 140#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864EC141 142#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864F0143 144#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864F4145 146#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864F8147 148#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE864FC149 150#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE86500151 152#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE86504153 154#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE86508155 156#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE8650C157 158#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE86510159 160#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE86514161 162#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE86518163 164#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE8651C165 166#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE86520167 168#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE86524169 170#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE86528171 172#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE8652C173 174#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE86530175 176#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE86534177 178#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE86538179 180#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE8653C181 182#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE86540183 184#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE86544185 186#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE86548187 188#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE8654C189 190#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE86550191 192#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE86554193 194#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86558195 196#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE8655C197 198#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE86560199 200#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86564201 202#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE86568203 204#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE8656C205 206#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86570207 208#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86574209 210#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE86578211 212#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE8657C213 214#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE86580215 216#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86584217 218#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86588219 220#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE8658C221 222#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE86590223 224#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE86594225 226#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86598227 228#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE8659C229 230#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE865A0231 232#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE865A4233 234#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE865A8235 236#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE865AC237 238#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE865B0239 240#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE865B4241 242#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE865B8243 244#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE865BC245 246#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE865C0247 248#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE865C4249 250#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE865C8251 252#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE865CC253 254#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE865D0255 256#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE865D4257 258#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE865D8259 260#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE865DC261 262#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE865E0263 264#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE865E4265 266#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE865E8267 268#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE865EC269 270#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE865F0271 272#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE865F4273 274#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE865F8275 276#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE865FC277 278#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE86600279 280#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE86604281 282#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86608283 284#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE8660C285 286#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE86610287 288#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86614289 290#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE86618291 292#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE8661C293 294#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86620295 296#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86624297 298#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE86628299 300#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE8662C301 302#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE86630303 304#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE86634305 306#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE86638307 308#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE8663C309 310#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE86640311 312#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE86644313 314#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE86648315 316#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE8664C317 318#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE86650319 320#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE86654321 322#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE86658323 324#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE8665C325 326#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86660327 328#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE86664329 330#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86668331 332#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE8666C333 334#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86670335 336#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE86674337 338#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE86678339 340#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE8667C341 342#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE86680343 344#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE86684345 346#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE86688347 348#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE8668C349 350#define mmTPC2_CFG_KERNEL_SRF_0 0xE86690351 352#define mmTPC2_CFG_KERNEL_SRF_1 0xE86694353 354#define mmTPC2_CFG_KERNEL_SRF_2 0xE86698355 356#define mmTPC2_CFG_KERNEL_SRF_3 0xE8669C357 358#define mmTPC2_CFG_KERNEL_SRF_4 0xE866A0359 360#define mmTPC2_CFG_KERNEL_SRF_5 0xE866A4361 362#define mmTPC2_CFG_KERNEL_SRF_6 0xE866A8363 364#define mmTPC2_CFG_KERNEL_SRF_7 0xE866AC365 366#define mmTPC2_CFG_KERNEL_SRF_8 0xE866B0367 368#define mmTPC2_CFG_KERNEL_SRF_9 0xE866B4369 370#define mmTPC2_CFG_KERNEL_SRF_10 0xE866B8371 372#define mmTPC2_CFG_KERNEL_SRF_11 0xE866BC373 374#define mmTPC2_CFG_KERNEL_SRF_12 0xE866C0375 376#define mmTPC2_CFG_KERNEL_SRF_13 0xE866C4377 378#define mmTPC2_CFG_KERNEL_SRF_14 0xE866C8379 380#define mmTPC2_CFG_KERNEL_SRF_15 0xE866CC381 382#define mmTPC2_CFG_KERNEL_SRF_16 0xE866D0383 384#define mmTPC2_CFG_KERNEL_SRF_17 0xE866D4385 386#define mmTPC2_CFG_KERNEL_SRF_18 0xE866D8387 388#define mmTPC2_CFG_KERNEL_SRF_19 0xE866DC389 390#define mmTPC2_CFG_KERNEL_SRF_20 0xE866E0391 392#define mmTPC2_CFG_KERNEL_SRF_21 0xE866E4393 394#define mmTPC2_CFG_KERNEL_SRF_22 0xE866E8395 396#define mmTPC2_CFG_KERNEL_SRF_23 0xE866EC397 398#define mmTPC2_CFG_KERNEL_SRF_24 0xE866F0399 400#define mmTPC2_CFG_KERNEL_SRF_25 0xE866F4401 402#define mmTPC2_CFG_KERNEL_SRF_26 0xE866F8403 404#define mmTPC2_CFG_KERNEL_SRF_27 0xE866FC405 406#define mmTPC2_CFG_KERNEL_SRF_28 0xE86700407 408#define mmTPC2_CFG_KERNEL_SRF_29 0xE86704409 410#define mmTPC2_CFG_KERNEL_SRF_30 0xE86708411 412#define mmTPC2_CFG_KERNEL_SRF_31 0xE8670C413 414#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE86710415 416#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86714417 418#define mmTPC2_CFG_RESERVED_DESC_END 0xE86738419 420#define mmTPC2_CFG_ROUND_CSR 0xE867FC421 422#define mmTPC2_CFG_TBUF_BASE_ADDR_LOW 0xE86800423 424#define mmTPC2_CFG_TBUF_BASE_ADDR_HIGH 0xE86804425 426#define mmTPC2_CFG_SEMAPHORE 0xE86808427 428#define mmTPC2_CFG_VFLAGS 0xE8680C429 430#define mmTPC2_CFG_SFLAGS 0xE86810431 432#define mmTPC2_CFG_LFSR_POLYNOM 0xE86818433 434#define mmTPC2_CFG_STATUS 0xE8681C435 436#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86820437 438#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86824439 440#define mmTPC2_CFG_SM_BASE_ADDRESS_LOW 0xE86828441 442#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8682C443 444#define mmTPC2_CFG_TPC_CMD 0xE86830445 446#define mmTPC2_CFG_TPC_EXECUTE 0xE86838447 448#define mmTPC2_CFG_TPC_STALL 0xE8683C449 450#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86840451 452#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86844453 454#define mmTPC2_CFG_MSS_CONFIG 0xE86854455 456#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86858457 458#define mmTPC2_CFG_TPC_INTR_MASK 0xE8685C459 460#define mmTPC2_CFG_TSB_CONFIG 0xE86860461 462#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00463 464#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04465 466#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08467 468#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C469 470#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10471 472#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14473 474#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE86A18475 476#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A1C477 478#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A20479 480#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE86A24481 482#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A28483 484#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A2C485 486#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE86A30487 488#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A34489 490#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A38491 492#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE86A3C493 494#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A40495 496#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A44497 498#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE86A48499 500#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A4C501 502#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A50503 504#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A54505 506#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A58507 508#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A5C509 510#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A60511 512#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE86A64513 514#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A68515 516#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A6C517 518#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE86A70519 520#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A74521 522#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A78523 524#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE86A7C525 526#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A80527 528#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A84529 530#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE86A88531 532#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A8C533 534#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A90535 536#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE86A94537 538#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A98539 540#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A9C541 542#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86AA0543 544#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86AA4545 546#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86AA8547 548#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86AAC549 550#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE86AB0551 552#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86AB4553 554#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86AB8555 556#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE86ABC557 558#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86AC0559 560#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86AC4561 562#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE86AC8563 564#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86ACC565 566#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86AD0567 568#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE86AD4569 570#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AD8571 572#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86ADC573 574#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE86AE0575 576#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AE4577 578#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AE8579 580#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AEC581 582#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AF0583 584#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AF4585 586#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86AF8587 588#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE86AFC589 590#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86B00591 592#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86B04593 594#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE86B08595 596#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86B0C597 598#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86B10599 600#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE86B14601 602#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86B18603 604#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86B1C605 606#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE86B20607 608#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86B24609 610#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86B28611 612#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE86B2C613 614#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86B30615 616#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86B34617 618#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86B38619 620#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86B3C621 622#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86B40623 624#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86B44625 626#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE86B48627 628#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86B4C629 630#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86B50631 632#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE86B54633 634#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B58635 636#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B5C637 638#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE86B60639 640#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B64641 642#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B68643 644#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE86B6C645 646#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B70647 648#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B74649 650#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE86B78651 652#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B7C653 654#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B80655 656#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B84657 658#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B88659 660#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B8C661 662#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B90663 664#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE86B94665 666#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B98667 668#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B9C669 670#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE86BA0671 672#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86BA4673 674#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86BA8675 676#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE86BAC677 678#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86BB0679 680#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86BB4681 682#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE86BB8683 684#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86BBC685 686#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86BC0687 688#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE86BC4689 690#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86BC8691 692#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86BCC693 694#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86BD0695 696#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86BD4697 698#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86BD8699 700#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86BDC701 702#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE86BE0703 704#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86BE4705 706#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86BE8707 708#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE86BEC709 710#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86BF0711 712#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86BF4713 714#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE86BF8715 716#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86BFC717 718#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86C00719 720#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE86C04721 722#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86C08723 724#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86C0C725 726#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE86C10727 728#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86C14729 730#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86C18731 732#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86C1C733 734#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86C20735 736#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86C24737 738#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86C28739 740#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE86C2C741 742#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86C30743 744#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86C34745 746#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE86C38747 748#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86C3C749 750#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86C40751 752#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE86C44753 754#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86C48755 756#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86C4C757 758#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE86C50759 760#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86C54761 762#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86C58763 764#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE86C5C765 766#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86C60767 768#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86C64769 770#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86C68771 772#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86C6C773 774#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86C70775 776#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86C74777 778#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86C78779 780#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86C7C781 782#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86C80783 784#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86C84785 786#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86C88787 788#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86C8C789 790#define mmTPC2_CFG_QM_SRF_0 0xE86C90791 792#define mmTPC2_CFG_QM_SRF_1 0xE86C94793 794#define mmTPC2_CFG_QM_SRF_2 0xE86C98795 796#define mmTPC2_CFG_QM_SRF_3 0xE86C9C797 798#define mmTPC2_CFG_QM_SRF_4 0xE86CA0799 800#define mmTPC2_CFG_QM_SRF_5 0xE86CA4801 802#define mmTPC2_CFG_QM_SRF_6 0xE86CA8803 804#define mmTPC2_CFG_QM_SRF_7 0xE86CAC805 806#define mmTPC2_CFG_QM_SRF_8 0xE86CB0807 808#define mmTPC2_CFG_QM_SRF_9 0xE86CB4809 810#define mmTPC2_CFG_QM_SRF_10 0xE86CB8811 812#define mmTPC2_CFG_QM_SRF_11 0xE86CBC813 814#define mmTPC2_CFG_QM_SRF_12 0xE86CC0815 816#define mmTPC2_CFG_QM_SRF_13 0xE86CC4817 818#define mmTPC2_CFG_QM_SRF_14 0xE86CC8819 820#define mmTPC2_CFG_QM_SRF_15 0xE86CCC821 822#define mmTPC2_CFG_QM_SRF_16 0xE86CD0823 824#define mmTPC2_CFG_QM_SRF_17 0xE86CD4825 826#define mmTPC2_CFG_QM_SRF_18 0xE86CD8827 828#define mmTPC2_CFG_QM_SRF_19 0xE86CDC829 830#define mmTPC2_CFG_QM_SRF_20 0xE86CE0831 832#define mmTPC2_CFG_QM_SRF_21 0xE86CE4833 834#define mmTPC2_CFG_QM_SRF_22 0xE86CE8835 836#define mmTPC2_CFG_QM_SRF_23 0xE86CEC837 838#define mmTPC2_CFG_QM_SRF_24 0xE86CF0839 840#define mmTPC2_CFG_QM_SRF_25 0xE86CF4841 842#define mmTPC2_CFG_QM_SRF_26 0xE86CF8843 844#define mmTPC2_CFG_QM_SRF_27 0xE86CFC845 846#define mmTPC2_CFG_QM_SRF_28 0xE86D00847 848#define mmTPC2_CFG_QM_SRF_29 0xE86D04849 850#define mmTPC2_CFG_QM_SRF_30 0xE86D08851 852#define mmTPC2_CFG_QM_SRF_31 0xE86D0C853 854#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86D10855 856#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D14857 858#define mmTPC2_CFG_ARUSER 0xE86D18859 860#define mmTPC2_CFG_AWUSER 0xE86D1C861 862#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE86E00863 864#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE86E04865 866#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE86E08867 868#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE86E0C869 870#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE86E10871 872#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE86E14873 874#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE86E18875 876#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE86E1C877 878#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE86E20879 880#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE86E24881 882#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE86E28883 884#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE86E2C885 886#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */887