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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC2_CMDQ_REGS_H_14#define ASIC_REG_TPC2_CMDQ_REGS_H_15 16/*17 *****************************************18 * TPC2_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22#define mmTPC2_CMDQ_GLBL_CFG0 0xE8900023 24#define mmTPC2_CMDQ_GLBL_CFG1 0xE8900425 26#define mmTPC2_CMDQ_GLBL_PROT 0xE8900827 28#define mmTPC2_CMDQ_GLBL_ERR_CFG 0xE8900C29 30#define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO 0xE8901031 32#define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI 0xE8901433 34#define mmTPC2_CMDQ_GLBL_ERR_WDATA 0xE8901835 36#define mmTPC2_CMDQ_GLBL_SECURE_PROPS 0xE8901C37 38#define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS 0xE8902039 40#define mmTPC2_CMDQ_GLBL_STS0 0xE8902441 42#define mmTPC2_CMDQ_GLBL_STS1 0xE8902843 44#define mmTPC2_CMDQ_CQ_CFG0 0xE890B045 46#define mmTPC2_CMDQ_CQ_CFG1 0xE890B447 48#define mmTPC2_CMDQ_CQ_ARUSER 0xE890B849 50#define mmTPC2_CMDQ_CQ_PTR_LO 0xE890C051 52#define mmTPC2_CMDQ_CQ_PTR_HI 0xE890C453 54#define mmTPC2_CMDQ_CQ_TSIZE 0xE890C855 56#define mmTPC2_CMDQ_CQ_CTL 0xE890CC57 58#define mmTPC2_CMDQ_CQ_PTR_LO_STS 0xE890D459 60#define mmTPC2_CMDQ_CQ_PTR_HI_STS 0xE890D861 62#define mmTPC2_CMDQ_CQ_TSIZE_STS 0xE890DC63 64#define mmTPC2_CMDQ_CQ_CTL_STS 0xE890E065 66#define mmTPC2_CMDQ_CQ_STS0 0xE890E467 68#define mmTPC2_CMDQ_CQ_STS1 0xE890E869 70#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN 0xE890F071 72#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE890F473 74#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT 0xE890F875 76#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE890FC77 78#define mmTPC2_CMDQ_CQ_IFIFO_CNT 0xE8910879 80#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE8912081 82#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE8912483 84#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE8912885 86#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE8912C87 88#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE8913089 90#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE8913491 92#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE8913893 94#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE8913C95 96#define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE8914097 98#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE8914499 100#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE89148101 102#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE8914C103 104#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE89150105 106#define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE89154107 108#define mmTPC2_CMDQ_CP_FENCE0_RDATA 0xE89158109 110#define mmTPC2_CMDQ_CP_FENCE1_RDATA 0xE8915C111 112#define mmTPC2_CMDQ_CP_FENCE2_RDATA 0xE89160113 114#define mmTPC2_CMDQ_CP_FENCE3_RDATA 0xE89164115 116#define mmTPC2_CMDQ_CP_FENCE0_CNT 0xE89168117 118#define mmTPC2_CMDQ_CP_FENCE1_CNT 0xE8916C119 120#define mmTPC2_CMDQ_CP_FENCE2_CNT 0xE89170121 122#define mmTPC2_CMDQ_CP_FENCE3_CNT 0xE89174123 124#define mmTPC2_CMDQ_CP_STS 0xE89178125 126#define mmTPC2_CMDQ_CP_CURRENT_INST_LO 0xE8917C127 128#define mmTPC2_CMDQ_CP_CURRENT_INST_HI 0xE89180129 130#define mmTPC2_CMDQ_CP_BARRIER_CFG 0xE89184131 132#define mmTPC2_CMDQ_CP_DBG_0 0xE89188133 134#define mmTPC2_CMDQ_CQ_BUF_ADDR 0xE89308135 136#define mmTPC2_CMDQ_CQ_BUF_RDATA 0xE8930C137 138#endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */139