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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC3_CFG_REGS_H_14#define ASIC_REG_TPC3_CFG_REGS_H_15 16/*17 *****************************************18 * TPC3_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC640023 24#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC640425 26#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC640827 28#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C29 30#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC641031 32#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC641433 34#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xEC641835 36#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC641C37 38#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC642039 40#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xEC642441 42#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC642843 44#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC642C45 46#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xEC643047 48#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC643449 50#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC643851 52#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xEC643C53 54#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC644055 56#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC644457 58#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xEC644859 60#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC644C61 62#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC645063 64#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC645465 66#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC645867 68#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC645C69 70#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC646071 72#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xEC646473 74#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC646875 76#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC646C77 78#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xEC647079 80#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC647481 82#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC647883 84#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xEC647C85 86#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC648087 88#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC648489 90#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xEC648891 92#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC648C93 94#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC649095 96#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xEC649497 98#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC649899 100#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC649C101 102#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC64A0103 104#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC64A4105 106#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC64A8107 108#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC64AC109 110#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xEC64B0111 112#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC64B4113 114#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC64B8115 116#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xEC64BC117 118#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC64C0119 120#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC64C4121 122#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xEC64C8123 124#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC64CC125 126#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC64D0127 128#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xEC64D4129 130#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64D8131 132#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64DC133 134#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xEC64E0135 136#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64E4137 138#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64E8139 140#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64EC141 142#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64F0143 144#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64F4145 146#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64F8147 148#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xEC64FC149 150#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC6500151 152#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC6504153 154#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6508155 156#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC650C157 158#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC6510159 160#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6514161 162#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC6518163 164#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC651C165 166#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6520167 168#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC6524169 170#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC6528171 172#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xEC652C173 174#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC6530175 176#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC6534177 178#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC6538179 180#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC653C181 182#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC6540183 184#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC6544185 186#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6548187 188#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC654C189 190#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC6550191 192#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6554193 194#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6558195 196#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC655C197 198#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6560199 200#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6564201 202#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC6568203 204#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xEC656C205 206#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6570207 208#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6574209 210#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6578211 212#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC657C213 214#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC6580215 216#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6584217 218#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6588219 220#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC658C221 222#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC6590223 224#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6594225 226#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6598227 228#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC659C229 230#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xEC65A0231 232#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC65A4233 234#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC65A8235 236#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xEC65AC237 238#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC65B0239 240#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC65B4241 242#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xEC65B8243 244#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC65BC245 246#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC65C0247 248#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xEC65C4249 250#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC65C8251 252#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC65CC253 254#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC65D0255 256#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC65D4257 258#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC65D8259 260#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC65DC261 262#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xEC65E0263 264#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC65E4265 266#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC65E8267 268#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xEC65EC269 270#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC65F0271 272#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC65F4273 274#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xEC65F8275 276#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC65FC277 278#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC6600279 280#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6604281 282#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6608283 284#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC660C285 286#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6610287 288#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6614289 290#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC6618291 292#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC661C293 294#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6620295 296#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6624297 298#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC6628299 300#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xEC662C301 302#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC6630303 304#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC6634305 306#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6638307 308#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC663C309 310#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC6640311 312#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6644313 314#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC6648315 316#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC664C317 318#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6650319 320#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC6654321 322#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC6658323 324#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xEC665C325 326#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6660327 328#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC6664329 330#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6668331 332#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC666C333 334#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6670335 336#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC6674337 338#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC6678339 340#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC667C341 342#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC6680343 344#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC6684345 346#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC6688347 348#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC668C349 350#define mmTPC3_CFG_KERNEL_SRF_0 0xEC6690351 352#define mmTPC3_CFG_KERNEL_SRF_1 0xEC6694353 354#define mmTPC3_CFG_KERNEL_SRF_2 0xEC6698355 356#define mmTPC3_CFG_KERNEL_SRF_3 0xEC669C357 358#define mmTPC3_CFG_KERNEL_SRF_4 0xEC66A0359 360#define mmTPC3_CFG_KERNEL_SRF_5 0xEC66A4361 362#define mmTPC3_CFG_KERNEL_SRF_6 0xEC66A8363 364#define mmTPC3_CFG_KERNEL_SRF_7 0xEC66AC365 366#define mmTPC3_CFG_KERNEL_SRF_8 0xEC66B0367 368#define mmTPC3_CFG_KERNEL_SRF_9 0xEC66B4369 370#define mmTPC3_CFG_KERNEL_SRF_10 0xEC66B8371 372#define mmTPC3_CFG_KERNEL_SRF_11 0xEC66BC373 374#define mmTPC3_CFG_KERNEL_SRF_12 0xEC66C0375 376#define mmTPC3_CFG_KERNEL_SRF_13 0xEC66C4377 378#define mmTPC3_CFG_KERNEL_SRF_14 0xEC66C8379 380#define mmTPC3_CFG_KERNEL_SRF_15 0xEC66CC381 382#define mmTPC3_CFG_KERNEL_SRF_16 0xEC66D0383 384#define mmTPC3_CFG_KERNEL_SRF_17 0xEC66D4385 386#define mmTPC3_CFG_KERNEL_SRF_18 0xEC66D8387 388#define mmTPC3_CFG_KERNEL_SRF_19 0xEC66DC389 390#define mmTPC3_CFG_KERNEL_SRF_20 0xEC66E0391 392#define mmTPC3_CFG_KERNEL_SRF_21 0xEC66E4393 394#define mmTPC3_CFG_KERNEL_SRF_22 0xEC66E8395 396#define mmTPC3_CFG_KERNEL_SRF_23 0xEC66EC397 398#define mmTPC3_CFG_KERNEL_SRF_24 0xEC66F0399 400#define mmTPC3_CFG_KERNEL_SRF_25 0xEC66F4401 402#define mmTPC3_CFG_KERNEL_SRF_26 0xEC66F8403 404#define mmTPC3_CFG_KERNEL_SRF_27 0xEC66FC405 406#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6700407 408#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6704409 410#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6708411 412#define mmTPC3_CFG_KERNEL_SRF_31 0xEC670C413 414#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC6710415 416#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6714417 418#define mmTPC3_CFG_RESERVED_DESC_END 0xEC6738419 420#define mmTPC3_CFG_ROUND_CSR 0xEC67FC421 422#define mmTPC3_CFG_TBUF_BASE_ADDR_LOW 0xEC6800423 424#define mmTPC3_CFG_TBUF_BASE_ADDR_HIGH 0xEC6804425 426#define mmTPC3_CFG_SEMAPHORE 0xEC6808427 428#define mmTPC3_CFG_VFLAGS 0xEC680C429 430#define mmTPC3_CFG_SFLAGS 0xEC6810431 432#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6818433 434#define mmTPC3_CFG_STATUS 0xEC681C435 436#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6820437 438#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6824439 440#define mmTPC3_CFG_SM_BASE_ADDRESS_LOW 0xEC6828441 442#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC682C443 444#define mmTPC3_CFG_TPC_CMD 0xEC6830445 446#define mmTPC3_CFG_TPC_EXECUTE 0xEC6838447 448#define mmTPC3_CFG_TPC_STALL 0xEC683C449 450#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6840451 452#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6844453 454#define mmTPC3_CFG_MSS_CONFIG 0xEC6854455 456#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6858457 458#define mmTPC3_CFG_TPC_INTR_MASK 0xEC685C459 460#define mmTPC3_CFG_TSB_CONFIG 0xEC6860461 462#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00463 464#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04465 466#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08467 468#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C469 470#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10471 472#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14473 474#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xEC6A18475 476#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A1C477 478#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A20479 480#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xEC6A24481 482#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A28483 484#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A2C485 486#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xEC6A30487 488#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A34489 490#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A38491 492#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xEC6A3C493 494#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A40495 496#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A44497 498#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xEC6A48499 500#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A4C501 502#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A50503 504#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A54505 506#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A58507 508#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A5C509 510#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A60511 512#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xEC6A64513 514#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A68515 516#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A6C517 518#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xEC6A70519 520#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A74521 522#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A78523 524#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xEC6A7C525 526#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A80527 528#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A84529 530#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xEC6A88531 532#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A8C533 534#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A90535 536#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xEC6A94537 538#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A98539 540#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A9C541 542#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6AA0543 544#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6AA4545 546#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6AA8547 548#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6AAC549 550#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xEC6AB0551 552#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6AB4553 554#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6AB8555 556#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xEC6ABC557 558#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6AC0559 560#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6AC4561 562#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xEC6AC8563 564#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6ACC565 566#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6AD0567 568#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xEC6AD4569 570#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AD8571 572#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6ADC573 574#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xEC6AE0575 576#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AE4577 578#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AE8579 580#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AEC581 582#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AF0583 584#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AF4585 586#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6AF8587 588#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xEC6AFC589 590#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6B00591 592#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6B04593 594#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xEC6B08595 596#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6B0C597 598#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6B10599 600#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xEC6B14601 602#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6B18603 604#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6B1C605 606#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xEC6B20607 608#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6B24609 610#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6B28611 612#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xEC6B2C613 614#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6B30615 616#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6B34617 618#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6B38619 620#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6B3C621 622#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6B40623 624#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6B44625 626#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xEC6B48627 628#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6B4C629 630#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6B50631 632#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xEC6B54633 634#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B58635 636#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B5C637 638#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xEC6B60639 640#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B64641 642#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B68643 644#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xEC6B6C645 646#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B70647 648#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B74649 650#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xEC6B78651 652#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B7C653 654#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B80655 656#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B84657 658#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B88659 660#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B8C661 662#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B90663 664#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xEC6B94665 666#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B98667 668#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B9C669 670#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xEC6BA0671 672#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6BA4673 674#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6BA8675 676#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xEC6BAC677 678#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6BB0679 680#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6BB4681 682#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xEC6BB8683 684#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6BBC685 686#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6BC0687 688#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xEC6BC4689 690#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6BC8691 692#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6BCC693 694#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6BD0695 696#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6BD4697 698#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6BD8699 700#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6BDC701 702#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xEC6BE0703 704#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6BE4705 706#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6BE8707 708#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xEC6BEC709 710#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6BF0711 712#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6BF4713 714#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xEC6BF8715 716#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6BFC717 718#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6C00719 720#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xEC6C04721 722#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6C08723 724#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6C0C725 726#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xEC6C10727 728#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6C14729 730#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6C18731 732#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6C1C733 734#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6C20735 736#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6C24737 738#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6C28739 740#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xEC6C2C741 742#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6C30743 744#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6C34745 746#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xEC6C38747 748#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6C3C749 750#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6C40751 752#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xEC6C44753 754#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6C48755 756#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6C4C757 758#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xEC6C50759 760#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6C54761 762#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6C58763 764#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xEC6C5C765 766#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6C60767 768#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6C64769 770#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6C68771 772#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6C6C773 774#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6C70775 776#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6C74777 778#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6C78779 780#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6C7C781 782#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6C80783 784#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6C84785 786#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6C88787 788#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6C8C789 790#define mmTPC3_CFG_QM_SRF_0 0xEC6C90791 792#define mmTPC3_CFG_QM_SRF_1 0xEC6C94793 794#define mmTPC3_CFG_QM_SRF_2 0xEC6C98795 796#define mmTPC3_CFG_QM_SRF_3 0xEC6C9C797 798#define mmTPC3_CFG_QM_SRF_4 0xEC6CA0799 800#define mmTPC3_CFG_QM_SRF_5 0xEC6CA4801 802#define mmTPC3_CFG_QM_SRF_6 0xEC6CA8803 804#define mmTPC3_CFG_QM_SRF_7 0xEC6CAC805 806#define mmTPC3_CFG_QM_SRF_8 0xEC6CB0807 808#define mmTPC3_CFG_QM_SRF_9 0xEC6CB4809 810#define mmTPC3_CFG_QM_SRF_10 0xEC6CB8811 812#define mmTPC3_CFG_QM_SRF_11 0xEC6CBC813 814#define mmTPC3_CFG_QM_SRF_12 0xEC6CC0815 816#define mmTPC3_CFG_QM_SRF_13 0xEC6CC4817 818#define mmTPC3_CFG_QM_SRF_14 0xEC6CC8819 820#define mmTPC3_CFG_QM_SRF_15 0xEC6CCC821 822#define mmTPC3_CFG_QM_SRF_16 0xEC6CD0823 824#define mmTPC3_CFG_QM_SRF_17 0xEC6CD4825 826#define mmTPC3_CFG_QM_SRF_18 0xEC6CD8827 828#define mmTPC3_CFG_QM_SRF_19 0xEC6CDC829 830#define mmTPC3_CFG_QM_SRF_20 0xEC6CE0831 832#define mmTPC3_CFG_QM_SRF_21 0xEC6CE4833 834#define mmTPC3_CFG_QM_SRF_22 0xEC6CE8835 836#define mmTPC3_CFG_QM_SRF_23 0xEC6CEC837 838#define mmTPC3_CFG_QM_SRF_24 0xEC6CF0839 840#define mmTPC3_CFG_QM_SRF_25 0xEC6CF4841 842#define mmTPC3_CFG_QM_SRF_26 0xEC6CF8843 844#define mmTPC3_CFG_QM_SRF_27 0xEC6CFC845 846#define mmTPC3_CFG_QM_SRF_28 0xEC6D00847 848#define mmTPC3_CFG_QM_SRF_29 0xEC6D04849 850#define mmTPC3_CFG_QM_SRF_30 0xEC6D08851 852#define mmTPC3_CFG_QM_SRF_31 0xEC6D0C853 854#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6D10855 856#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D14857 858#define mmTPC3_CFG_ARUSER 0xEC6D18859 860#define mmTPC3_CFG_AWUSER 0xEC6D1C861 862#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC6E00863 864#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC6E04865 866#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC6E08867 868#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC6E0C869 870#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC6E10871 872#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC6E14873 874#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC6E18875 876#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC6E1C877 878#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC6E20879 880#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC6E24881 882#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC6E28883 884#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC6E2C885 886#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */887