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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 **       DO NOT EDIT BELOW        **11 ************************************/12 13#ifndef ASIC_REG_TPC3_QM_REGS_H_14#define ASIC_REG_TPC3_QM_REGS_H_15 16/*17 *****************************************18 *   TPC3_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmTPC3_QM_GLBL_CFG0                                          0xEC800023 24#define mmTPC3_QM_GLBL_CFG1                                          0xEC800425 26#define mmTPC3_QM_GLBL_PROT                                          0xEC800827 28#define mmTPC3_QM_GLBL_ERR_CFG                                       0xEC800C29 30#define mmTPC3_QM_GLBL_ERR_ADDR_LO                                   0xEC801031 32#define mmTPC3_QM_GLBL_ERR_ADDR_HI                                   0xEC801433 34#define mmTPC3_QM_GLBL_ERR_WDATA                                     0xEC801835 36#define mmTPC3_QM_GLBL_SECURE_PROPS                                  0xEC801C37 38#define mmTPC3_QM_GLBL_NON_SECURE_PROPS                              0xEC802039 40#define mmTPC3_QM_GLBL_STS0                                          0xEC802441 42#define mmTPC3_QM_GLBL_STS1                                          0xEC802843 44#define mmTPC3_QM_PQ_BASE_LO                                         0xEC806045 46#define mmTPC3_QM_PQ_BASE_HI                                         0xEC806447 48#define mmTPC3_QM_PQ_SIZE                                            0xEC806849 50#define mmTPC3_QM_PQ_PI                                              0xEC806C51 52#define mmTPC3_QM_PQ_CI                                              0xEC807053 54#define mmTPC3_QM_PQ_CFG0                                            0xEC807455 56#define mmTPC3_QM_PQ_CFG1                                            0xEC807857 58#define mmTPC3_QM_PQ_ARUSER                                          0xEC807C59 60#define mmTPC3_QM_PQ_PUSH0                                           0xEC808061 62#define mmTPC3_QM_PQ_PUSH1                                           0xEC808463 64#define mmTPC3_QM_PQ_PUSH2                                           0xEC808865 66#define mmTPC3_QM_PQ_PUSH3                                           0xEC808C67 68#define mmTPC3_QM_PQ_STS0                                            0xEC809069 70#define mmTPC3_QM_PQ_STS1                                            0xEC809471 72#define mmTPC3_QM_PQ_RD_RATE_LIM_EN                                  0xEC80A073 74#define mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN                           0xEC80A475 76#define mmTPC3_QM_PQ_RD_RATE_LIM_SAT                                 0xEC80A877 78#define mmTPC3_QM_PQ_RD_RATE_LIM_TOUT                                0xEC80AC79 80#define mmTPC3_QM_CQ_CFG0                                            0xEC80B081 82#define mmTPC3_QM_CQ_CFG1                                            0xEC80B483 84#define mmTPC3_QM_CQ_ARUSER                                          0xEC80B885 86#define mmTPC3_QM_CQ_PTR_LO                                          0xEC80C087 88#define mmTPC3_QM_CQ_PTR_HI                                          0xEC80C489 90#define mmTPC3_QM_CQ_TSIZE                                           0xEC80C891 92#define mmTPC3_QM_CQ_CTL                                             0xEC80CC93 94#define mmTPC3_QM_CQ_PTR_LO_STS                                      0xEC80D495 96#define mmTPC3_QM_CQ_PTR_HI_STS                                      0xEC80D897 98#define mmTPC3_QM_CQ_TSIZE_STS                                       0xEC80DC99 100#define mmTPC3_QM_CQ_CTL_STS                                         0xEC80E0101 102#define mmTPC3_QM_CQ_STS0                                            0xEC80E4103 104#define mmTPC3_QM_CQ_STS1                                            0xEC80E8105 106#define mmTPC3_QM_CQ_RD_RATE_LIM_EN                                  0xEC80F0107 108#define mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN                           0xEC80F4109 110#define mmTPC3_QM_CQ_RD_RATE_LIM_SAT                                 0xEC80F8111 112#define mmTPC3_QM_CQ_RD_RATE_LIM_TOUT                                0xEC80FC113 114#define mmTPC3_QM_CQ_IFIFO_CNT                                       0xEC8108115 116#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO                               0xEC8120117 118#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI                               0xEC8124119 120#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO                               0xEC8128121 122#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI                               0xEC812C123 124#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO                               0xEC8130125 126#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI                               0xEC8134127 128#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO                               0xEC8138129 130#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI                               0xEC813C131 132#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET                               0xEC8140133 134#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET                         0xEC8144135 136#define mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET                         0xEC8148137 138#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET                         0xEC814C139 140#define mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET                         0xEC8150141 142#define mmTPC3_QM_CP_LDMA_COMMIT_OFFSET                              0xEC8154143 144#define mmTPC3_QM_CP_FENCE0_RDATA                                    0xEC8158145 146#define mmTPC3_QM_CP_FENCE1_RDATA                                    0xEC815C147 148#define mmTPC3_QM_CP_FENCE2_RDATA                                    0xEC8160149 150#define mmTPC3_QM_CP_FENCE3_RDATA                                    0xEC8164151 152#define mmTPC3_QM_CP_FENCE0_CNT                                      0xEC8168153 154#define mmTPC3_QM_CP_FENCE1_CNT                                      0xEC816C155 156#define mmTPC3_QM_CP_FENCE2_CNT                                      0xEC8170157 158#define mmTPC3_QM_CP_FENCE3_CNT                                      0xEC8174159 160#define mmTPC3_QM_CP_STS                                             0xEC8178161 162#define mmTPC3_QM_CP_CURRENT_INST_LO                                 0xEC817C163 164#define mmTPC3_QM_CP_CURRENT_INST_HI                                 0xEC8180165 166#define mmTPC3_QM_CP_BARRIER_CFG                                     0xEC8184167 168#define mmTPC3_QM_CP_DBG_0                                           0xEC8188169 170#define mmTPC3_QM_PQ_BUF_ADDR                                        0xEC8300171 172#define mmTPC3_QM_PQ_BUF_RDATA                                       0xEC8304173 174#define mmTPC3_QM_CQ_BUF_ADDR                                        0xEC8308175 176#define mmTPC3_QM_CQ_BUF_RDATA                                       0xEC830C177 178#endif /* ASIC_REG_TPC3_QM_REGS_H_ */179