887 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC4_CFG_REGS_H_14#define ASIC_REG_TPC4_CFG_REGS_H_15 16/*17 *****************************************18 * TPC4_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF0640023 24#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF0640425 26#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF0640827 28#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C29 30#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF0641031 32#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF0641433 34#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF0641835 36#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C37 38#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0642039 40#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF0642441 42#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF0642843 44#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C45 46#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF0643047 48#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF0643449 50#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0643851 52#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C53 54#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF0644055 56#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF0644457 58#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF0644859 60#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C61 62#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0645063 64#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF0645465 66#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF0645867 68#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C69 70#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0646071 72#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF0646473 74#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF0646875 76#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C77 78#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF0647079 80#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF0647481 82#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0647883 84#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C85 86#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF0648087 88#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF0648489 90#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF0648891 92#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C93 94#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0649095 96#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF0649497 98#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF0649899 100#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C101 102#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0103 104#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4105 106#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8107 108#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC109 110#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0111 112#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4113 114#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8115 116#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC117 118#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0119 120#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4121 122#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8123 124#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC125 126#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0127 128#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4129 130#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8131 132#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC133 134#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0135 136#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4137 138#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8139 140#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC141 142#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0143 144#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4145 146#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8147 148#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC149 150#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500151 152#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504153 154#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508155 156#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C157 158#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510159 160#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514161 162#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518163 164#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C165 166#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520167 168#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524169 170#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528171 172#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C173 174#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530175 176#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534177 178#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538179 180#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C181 182#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540183 184#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544185 186#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548187 188#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C189 190#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550191 192#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554193 194#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558195 196#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C197 198#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560199 200#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564201 202#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568203 204#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C205 206#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570207 208#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574209 210#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578211 212#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C213 214#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580215 216#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584217 218#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588219 220#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C221 222#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590223 224#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594225 226#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598227 228#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C229 230#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0231 232#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4233 234#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8235 236#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC237 238#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0239 240#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4241 242#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8243 244#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC245 246#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0247 248#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4249 250#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8251 252#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC253 254#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0255 256#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4257 258#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8259 260#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC261 262#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0263 264#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4265 266#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8267 268#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC269 270#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0271 272#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4273 274#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8275 276#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC277 278#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600279 280#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604281 282#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608283 284#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C285 286#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610287 288#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614289 290#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618291 292#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C293 294#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620295 296#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624297 298#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628299 300#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C301 302#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630303 304#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634305 306#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638307 308#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C309 310#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640311 312#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644313 314#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648315 316#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C317 318#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650319 320#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654321 322#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658323 324#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C325 326#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660327 328#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664329 330#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668331 332#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C333 334#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670335 336#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674337 338#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678339 340#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C341 342#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680343 344#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684345 346#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688347 348#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C349 350#define mmTPC4_CFG_KERNEL_SRF_0 0xF06690351 352#define mmTPC4_CFG_KERNEL_SRF_1 0xF06694353 354#define mmTPC4_CFG_KERNEL_SRF_2 0xF06698355 356#define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C357 358#define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0359 360#define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4361 362#define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8363 364#define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC365 366#define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0367 368#define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4369 370#define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8371 372#define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC373 374#define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0375 376#define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4377 378#define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8379 380#define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC381 382#define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0383 384#define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4385 386#define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8387 388#define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC389 390#define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0391 392#define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4393 394#define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8395 396#define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC397 398#define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0399 400#define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4401 402#define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8403 404#define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC405 406#define mmTPC4_CFG_KERNEL_SRF_28 0xF06700407 408#define mmTPC4_CFG_KERNEL_SRF_29 0xF06704409 410#define mmTPC4_CFG_KERNEL_SRF_30 0xF06708411 412#define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C413 414#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710415 416#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714417 418#define mmTPC4_CFG_RESERVED_DESC_END 0xF06738419 420#define mmTPC4_CFG_ROUND_CSR 0xF067FC421 422#define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800423 424#define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804425 426#define mmTPC4_CFG_SEMAPHORE 0xF06808427 428#define mmTPC4_CFG_VFLAGS 0xF0680C429 430#define mmTPC4_CFG_SFLAGS 0xF06810431 432#define mmTPC4_CFG_LFSR_POLYNOM 0xF06818433 434#define mmTPC4_CFG_STATUS 0xF0681C435 436#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820437 438#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824439 440#define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828441 442#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C443 444#define mmTPC4_CFG_TPC_CMD 0xF06830445 446#define mmTPC4_CFG_TPC_EXECUTE 0xF06838447 448#define mmTPC4_CFG_TPC_STALL 0xF0683C449 450#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840451 452#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844453 454#define mmTPC4_CFG_MSS_CONFIG 0xF06854455 456#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858457 458#define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C459 460#define mmTPC4_CFG_TSB_CONFIG 0xF06860461 462#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00463 464#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04465 466#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08467 468#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C469 470#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10471 472#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14473 474#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18475 476#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C477 478#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20479 480#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24481 482#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28483 484#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C485 486#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30487 488#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34489 490#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38491 492#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C493 494#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40495 496#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44497 498#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48499 500#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C501 502#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50503 504#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54505 506#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58507 508#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C509 510#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60511 512#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64513 514#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68515 516#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C517 518#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70519 520#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74521 522#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78523 524#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C525 526#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80527 528#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84529 530#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88531 532#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C533 534#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90535 536#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94537 538#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98539 540#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C541 542#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0543 544#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4545 546#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8547 548#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC549 550#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0551 552#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4553 554#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8555 556#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC557 558#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0559 560#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4561 562#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8563 564#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC565 566#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0567 568#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4569 570#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8571 572#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC573 574#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0575 576#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4577 578#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8579 580#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC581 582#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0583 584#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4585 586#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8587 588#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC589 590#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00591 592#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04593 594#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08595 596#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C597 598#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10599 600#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14601 602#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18603 604#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C605 606#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20607 608#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24609 610#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28611 612#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C613 614#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30615 616#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34617 618#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38619 620#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C621 622#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40623 624#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44625 626#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48627 628#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C629 630#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50631 632#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54633 634#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58635 636#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C637 638#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60639 640#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64641 642#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68643 644#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C645 646#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70647 648#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74649 650#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78651 652#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C653 654#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80655 656#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84657 658#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88659 660#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C661 662#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90663 664#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94665 666#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98667 668#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C669 670#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0671 672#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4673 674#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8675 676#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC677 678#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0679 680#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4681 682#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8683 684#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC685 686#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0687 688#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4689 690#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8691 692#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC693 694#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0695 696#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4697 698#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8699 700#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC701 702#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0703 704#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4705 706#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8707 708#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC709 710#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0711 712#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4713 714#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8715 716#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC717 718#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00719 720#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04721 722#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08723 724#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C725 726#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10727 728#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14729 730#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18731 732#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C733 734#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20735 736#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24737 738#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28739 740#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C741 742#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30743 744#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34745 746#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38747 748#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C749 750#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40751 752#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44753 754#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48755 756#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C757 758#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50759 760#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54761 762#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58763 764#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C765 766#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60767 768#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64769 770#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68771 772#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C773 774#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70775 776#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74777 778#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78779 780#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C781 782#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80783 784#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84785 786#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88787 788#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C789 790#define mmTPC4_CFG_QM_SRF_0 0xF06C90791 792#define mmTPC4_CFG_QM_SRF_1 0xF06C94793 794#define mmTPC4_CFG_QM_SRF_2 0xF06C98795 796#define mmTPC4_CFG_QM_SRF_3 0xF06C9C797 798#define mmTPC4_CFG_QM_SRF_4 0xF06CA0799 800#define mmTPC4_CFG_QM_SRF_5 0xF06CA4801 802#define mmTPC4_CFG_QM_SRF_6 0xF06CA8803 804#define mmTPC4_CFG_QM_SRF_7 0xF06CAC805 806#define mmTPC4_CFG_QM_SRF_8 0xF06CB0807 808#define mmTPC4_CFG_QM_SRF_9 0xF06CB4809 810#define mmTPC4_CFG_QM_SRF_10 0xF06CB8811 812#define mmTPC4_CFG_QM_SRF_11 0xF06CBC813 814#define mmTPC4_CFG_QM_SRF_12 0xF06CC0815 816#define mmTPC4_CFG_QM_SRF_13 0xF06CC4817 818#define mmTPC4_CFG_QM_SRF_14 0xF06CC8819 820#define mmTPC4_CFG_QM_SRF_15 0xF06CCC821 822#define mmTPC4_CFG_QM_SRF_16 0xF06CD0823 824#define mmTPC4_CFG_QM_SRF_17 0xF06CD4825 826#define mmTPC4_CFG_QM_SRF_18 0xF06CD8827 828#define mmTPC4_CFG_QM_SRF_19 0xF06CDC829 830#define mmTPC4_CFG_QM_SRF_20 0xF06CE0831 832#define mmTPC4_CFG_QM_SRF_21 0xF06CE4833 834#define mmTPC4_CFG_QM_SRF_22 0xF06CE8835 836#define mmTPC4_CFG_QM_SRF_23 0xF06CEC837 838#define mmTPC4_CFG_QM_SRF_24 0xF06CF0839 840#define mmTPC4_CFG_QM_SRF_25 0xF06CF4841 842#define mmTPC4_CFG_QM_SRF_26 0xF06CF8843 844#define mmTPC4_CFG_QM_SRF_27 0xF06CFC845 846#define mmTPC4_CFG_QM_SRF_28 0xF06D00847 848#define mmTPC4_CFG_QM_SRF_29 0xF06D04849 850#define mmTPC4_CFG_QM_SRF_30 0xF06D08851 852#define mmTPC4_CFG_QM_SRF_31 0xF06D0C853 854#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10855 856#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14857 858#define mmTPC4_CFG_ARUSER 0xF06D18859 860#define mmTPC4_CFG_AWUSER 0xF06D1C861 862#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00863 864#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04865 866#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08867 868#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C869 870#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10871 872#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14873 874#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18875 876#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C877 878#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20879 880#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24881 882#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28883 884#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C885 886#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */887