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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_14#define ASIC_REG_TPC4_CMDQ_REGS_H_15 16/*17 *****************************************18 * TPC4_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22#define mmTPC4_CMDQ_GLBL_CFG0 0xF0900023 24#define mmTPC4_CMDQ_GLBL_CFG1 0xF0900425 26#define mmTPC4_CMDQ_GLBL_PROT 0xF0900827 28#define mmTPC4_CMDQ_GLBL_ERR_CFG 0xF0900C29 30#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO 0xF0901031 32#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI 0xF0901433 34#define mmTPC4_CMDQ_GLBL_ERR_WDATA 0xF0901835 36#define mmTPC4_CMDQ_GLBL_SECURE_PROPS 0xF0901C37 38#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS 0xF0902039 40#define mmTPC4_CMDQ_GLBL_STS0 0xF0902441 42#define mmTPC4_CMDQ_GLBL_STS1 0xF0902843 44#define mmTPC4_CMDQ_CQ_CFG0 0xF090B045 46#define mmTPC4_CMDQ_CQ_CFG1 0xF090B447 48#define mmTPC4_CMDQ_CQ_ARUSER 0xF090B849 50#define mmTPC4_CMDQ_CQ_PTR_LO 0xF090C051 52#define mmTPC4_CMDQ_CQ_PTR_HI 0xF090C453 54#define mmTPC4_CMDQ_CQ_TSIZE 0xF090C855 56#define mmTPC4_CMDQ_CQ_CTL 0xF090CC57 58#define mmTPC4_CMDQ_CQ_PTR_LO_STS 0xF090D459 60#define mmTPC4_CMDQ_CQ_PTR_HI_STS 0xF090D861 62#define mmTPC4_CMDQ_CQ_TSIZE_STS 0xF090DC63 64#define mmTPC4_CMDQ_CQ_CTL_STS 0xF090E065 66#define mmTPC4_CMDQ_CQ_STS0 0xF090E467 68#define mmTPC4_CMDQ_CQ_STS1 0xF090E869 70#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN 0xF090F071 72#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF090F473 74#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT 0xF090F875 76#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF090FC77 78#define mmTPC4_CMDQ_CQ_IFIFO_CNT 0xF0910879 80#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF0912081 82#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF0912483 84#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF0912885 86#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF0912C87 88#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF0913089 90#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF0913491 92#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF0913893 94#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF0913C95 96#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF0914097 98#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF0914499 100#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF09148101 102#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF0914C103 104#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF09150105 106#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF09154107 108#define mmTPC4_CMDQ_CP_FENCE0_RDATA 0xF09158109 110#define mmTPC4_CMDQ_CP_FENCE1_RDATA 0xF0915C111 112#define mmTPC4_CMDQ_CP_FENCE2_RDATA 0xF09160113 114#define mmTPC4_CMDQ_CP_FENCE3_RDATA 0xF09164115 116#define mmTPC4_CMDQ_CP_FENCE0_CNT 0xF09168117 118#define mmTPC4_CMDQ_CP_FENCE1_CNT 0xF0916C119 120#define mmTPC4_CMDQ_CP_FENCE2_CNT 0xF09170121 122#define mmTPC4_CMDQ_CP_FENCE3_CNT 0xF09174123 124#define mmTPC4_CMDQ_CP_STS 0xF09178125 126#define mmTPC4_CMDQ_CP_CURRENT_INST_LO 0xF0917C127 128#define mmTPC4_CMDQ_CP_CURRENT_INST_HI 0xF09180129 130#define mmTPC4_CMDQ_CP_BARRIER_CFG 0xF09184131 132#define mmTPC4_CMDQ_CP_DBG_0 0xF09188133 134#define mmTPC4_CMDQ_CQ_BUF_ADDR 0xF09308135 136#define mmTPC4_CMDQ_CQ_BUF_RDATA 0xF0930C137 138#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */139