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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC5_CFG_REGS_H_14#define ASIC_REG_TPC5_CFG_REGS_H_15 16/*17 *****************************************18 * TPC5_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF4640023 24#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF4640425 26#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF4640827 28#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C29 30#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF4641031 32#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF4641433 34#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF4641835 36#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF4641C37 38#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4642039 40#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF4642441 42#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF4642843 44#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF4642C45 46#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF4643047 48#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF4643449 50#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4643851 52#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF4643C53 54#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF4644055 56#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF4644457 58#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF4644859 60#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF4644C61 62#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4645063 64#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF4645465 66#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF4645867 68#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF4645C69 70#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4646071 72#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF4646473 74#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF4646875 76#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF4646C77 78#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF4647079 80#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF4647481 82#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4647883 84#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF4647C85 86#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF4648087 88#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF4648489 90#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF4648891 92#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF4648C93 94#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4649095 96#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF4649497 98#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF4649899 100#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF4649C101 102#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF464A0103 104#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF464A4105 106#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF464A8107 108#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF464AC109 110#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF464B0111 112#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF464B4113 114#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF464B8115 116#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF464BC117 118#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF464C0119 120#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF464C4121 122#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF464C8123 124#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF464CC125 126#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF464D0127 128#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF464D4129 130#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464D8131 132#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464DC133 134#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF464E0135 136#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464E4137 138#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464E8139 140#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464EC141 142#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464F0143 144#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464F4145 146#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464F8147 148#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF464FC149 150#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF46500151 152#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF46504153 154#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF46508155 156#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF4650C157 158#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF46510159 160#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF46514161 162#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF46518163 164#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF4651C165 166#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF46520167 168#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF46524169 170#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF46528171 172#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF4652C173 174#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF46530175 176#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF46534177 178#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF46538179 180#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF4653C181 182#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF46540183 184#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF46544185 186#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF46548187 188#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF4654C189 190#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF46550191 192#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF46554193 194#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46558195 196#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF4655C197 198#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF46560199 200#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46564201 202#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF46568203 204#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF4656C205 206#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46570207 208#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46574209 210#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF46578211 212#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF4657C213 214#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF46580215 216#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46584217 218#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46588219 220#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF4658C221 222#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF46590223 224#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF46594225 226#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46598227 228#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF4659C229 230#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF465A0231 232#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF465A4233 234#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF465A8235 236#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF465AC237 238#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF465B0239 240#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF465B4241 242#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF465B8243 244#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF465BC245 246#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF465C0247 248#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF465C4249 250#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF465C8251 252#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF465CC253 254#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF465D0255 256#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF465D4257 258#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF465D8259 260#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF465DC261 262#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF465E0263 264#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF465E4265 266#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF465E8267 268#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF465EC269 270#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF465F0271 272#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF465F4273 274#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF465F8275 276#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF465FC277 278#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF46600279 280#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF46604281 282#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46608283 284#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF4660C285 286#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF46610287 288#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46614289 290#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF46618291 292#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF4661C293 294#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46620295 296#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46624297 298#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF46628299 300#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF4662C301 302#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF46630303 304#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF46634305 306#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF46638307 308#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF4663C309 310#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF46640311 312#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF46644313 314#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF46648315 316#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF4664C317 318#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF46650319 320#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF46654321 322#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF46658323 324#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF4665C325 326#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46660327 328#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF46664329 330#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46668331 332#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF4666C333 334#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46670335 336#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF46674337 338#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF46678339 340#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF4667C341 342#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF46680343 344#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF46684345 346#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF46688347 348#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF4668C349 350#define mmTPC5_CFG_KERNEL_SRF_0 0xF46690351 352#define mmTPC5_CFG_KERNEL_SRF_1 0xF46694353 354#define mmTPC5_CFG_KERNEL_SRF_2 0xF46698355 356#define mmTPC5_CFG_KERNEL_SRF_3 0xF4669C357 358#define mmTPC5_CFG_KERNEL_SRF_4 0xF466A0359 360#define mmTPC5_CFG_KERNEL_SRF_5 0xF466A4361 362#define mmTPC5_CFG_KERNEL_SRF_6 0xF466A8363 364#define mmTPC5_CFG_KERNEL_SRF_7 0xF466AC365 366#define mmTPC5_CFG_KERNEL_SRF_8 0xF466B0367 368#define mmTPC5_CFG_KERNEL_SRF_9 0xF466B4369 370#define mmTPC5_CFG_KERNEL_SRF_10 0xF466B8371 372#define mmTPC5_CFG_KERNEL_SRF_11 0xF466BC373 374#define mmTPC5_CFG_KERNEL_SRF_12 0xF466C0375 376#define mmTPC5_CFG_KERNEL_SRF_13 0xF466C4377 378#define mmTPC5_CFG_KERNEL_SRF_14 0xF466C8379 380#define mmTPC5_CFG_KERNEL_SRF_15 0xF466CC381 382#define mmTPC5_CFG_KERNEL_SRF_16 0xF466D0383 384#define mmTPC5_CFG_KERNEL_SRF_17 0xF466D4385 386#define mmTPC5_CFG_KERNEL_SRF_18 0xF466D8387 388#define mmTPC5_CFG_KERNEL_SRF_19 0xF466DC389 390#define mmTPC5_CFG_KERNEL_SRF_20 0xF466E0391 392#define mmTPC5_CFG_KERNEL_SRF_21 0xF466E4393 394#define mmTPC5_CFG_KERNEL_SRF_22 0xF466E8395 396#define mmTPC5_CFG_KERNEL_SRF_23 0xF466EC397 398#define mmTPC5_CFG_KERNEL_SRF_24 0xF466F0399 400#define mmTPC5_CFG_KERNEL_SRF_25 0xF466F4401 402#define mmTPC5_CFG_KERNEL_SRF_26 0xF466F8403 404#define mmTPC5_CFG_KERNEL_SRF_27 0xF466FC405 406#define mmTPC5_CFG_KERNEL_SRF_28 0xF46700407 408#define mmTPC5_CFG_KERNEL_SRF_29 0xF46704409 410#define mmTPC5_CFG_KERNEL_SRF_30 0xF46708411 412#define mmTPC5_CFG_KERNEL_SRF_31 0xF4670C413 414#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF46710415 416#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46714417 418#define mmTPC5_CFG_RESERVED_DESC_END 0xF46738419 420#define mmTPC5_CFG_ROUND_CSR 0xF467FC421 422#define mmTPC5_CFG_TBUF_BASE_ADDR_LOW 0xF46800423 424#define mmTPC5_CFG_TBUF_BASE_ADDR_HIGH 0xF46804425 426#define mmTPC5_CFG_SEMAPHORE 0xF46808427 428#define mmTPC5_CFG_VFLAGS 0xF4680C429 430#define mmTPC5_CFG_SFLAGS 0xF46810431 432#define mmTPC5_CFG_LFSR_POLYNOM 0xF46818433 434#define mmTPC5_CFG_STATUS 0xF4681C435 436#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46820437 438#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46824439 440#define mmTPC5_CFG_SM_BASE_ADDRESS_LOW 0xF46828441 442#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4682C443 444#define mmTPC5_CFG_TPC_CMD 0xF46830445 446#define mmTPC5_CFG_TPC_EXECUTE 0xF46838447 448#define mmTPC5_CFG_TPC_STALL 0xF4683C449 450#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46840451 452#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46844453 454#define mmTPC5_CFG_MSS_CONFIG 0xF46854455 456#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46858457 458#define mmTPC5_CFG_TPC_INTR_MASK 0xF4685C459 460#define mmTPC5_CFG_TSB_CONFIG 0xF46860461 462#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00463 464#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04465 466#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08467 468#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C469 470#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10471 472#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14473 474#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF46A18475 476#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A1C477 478#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A20479 480#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF46A24481 482#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A28483 484#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A2C485 486#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF46A30487 488#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A34489 490#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A38491 492#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF46A3C493 494#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A40495 496#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A44497 498#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF46A48499 500#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A4C501 502#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A50503 504#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A54505 506#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A58507 508#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A5C509 510#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A60511 512#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF46A64513 514#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A68515 516#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A6C517 518#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF46A70519 520#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A74521 522#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A78523 524#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF46A7C525 526#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A80527 528#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A84529 530#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF46A88531 532#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A8C533 534#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A90535 536#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF46A94537 538#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A98539 540#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A9C541 542#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46AA0543 544#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46AA4545 546#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46AA8547 548#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46AAC549 550#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF46AB0551 552#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46AB4553 554#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46AB8555 556#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF46ABC557 558#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46AC0559 560#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46AC4561 562#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF46AC8563 564#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46ACC565 566#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46AD0567 568#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF46AD4569 570#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AD8571 572#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46ADC573 574#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF46AE0575 576#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AE4577 578#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AE8579 580#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AEC581 582#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AF0583 584#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AF4585 586#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46AF8587 588#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF46AFC589 590#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46B00591 592#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46B04593 594#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF46B08595 596#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46B0C597 598#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46B10599 600#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF46B14601 602#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46B18603 604#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46B1C605 606#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF46B20607 608#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46B24609 610#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46B28611 612#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF46B2C613 614#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46B30615 616#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46B34617 618#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46B38619 620#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46B3C621 622#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46B40623 624#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46B44625 626#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF46B48627 628#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46B4C629 630#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46B50631 632#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF46B54633 634#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B58635 636#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B5C637 638#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF46B60639 640#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B64641 642#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B68643 644#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF46B6C645 646#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B70647 648#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B74649 650#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF46B78651 652#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B7C653 654#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B80655 656#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B84657 658#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B88659 660#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B8C661 662#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B90663 664#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF46B94665 666#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B98667 668#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B9C669 670#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF46BA0671 672#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46BA4673 674#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46BA8675 676#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF46BAC677 678#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46BB0679 680#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46BB4681 682#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF46BB8683 684#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46BBC685 686#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46BC0687 688#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF46BC4689 690#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46BC8691 692#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46BCC693 694#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46BD0695 696#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46BD4697 698#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46BD8699 700#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46BDC701 702#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF46BE0703 704#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46BE4705 706#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46BE8707 708#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF46BEC709 710#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46BF0711 712#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46BF4713 714#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF46BF8715 716#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46BFC717 718#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46C00719 720#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF46C04721 722#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46C08723 724#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46C0C725 726#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF46C10727 728#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46C14729 730#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46C18731 732#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46C1C733 734#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46C20735 736#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46C24737 738#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46C28739 740#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF46C2C741 742#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46C30743 744#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46C34745 746#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF46C38747 748#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46C3C749 750#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46C40751 752#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF46C44753 754#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46C48755 756#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46C4C757 758#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF46C50759 760#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46C54761 762#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46C58763 764#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF46C5C765 766#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46C60767 768#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46C64769 770#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46C68771 772#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46C6C773 774#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46C70775 776#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46C74777 778#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46C78779 780#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46C7C781 782#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46C80783 784#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46C84785 786#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46C88787 788#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46C8C789 790#define mmTPC5_CFG_QM_SRF_0 0xF46C90791 792#define mmTPC5_CFG_QM_SRF_1 0xF46C94793 794#define mmTPC5_CFG_QM_SRF_2 0xF46C98795 796#define mmTPC5_CFG_QM_SRF_3 0xF46C9C797 798#define mmTPC5_CFG_QM_SRF_4 0xF46CA0799 800#define mmTPC5_CFG_QM_SRF_5 0xF46CA4801 802#define mmTPC5_CFG_QM_SRF_6 0xF46CA8803 804#define mmTPC5_CFG_QM_SRF_7 0xF46CAC805 806#define mmTPC5_CFG_QM_SRF_8 0xF46CB0807 808#define mmTPC5_CFG_QM_SRF_9 0xF46CB4809 810#define mmTPC5_CFG_QM_SRF_10 0xF46CB8811 812#define mmTPC5_CFG_QM_SRF_11 0xF46CBC813 814#define mmTPC5_CFG_QM_SRF_12 0xF46CC0815 816#define mmTPC5_CFG_QM_SRF_13 0xF46CC4817 818#define mmTPC5_CFG_QM_SRF_14 0xF46CC8819 820#define mmTPC5_CFG_QM_SRF_15 0xF46CCC821 822#define mmTPC5_CFG_QM_SRF_16 0xF46CD0823 824#define mmTPC5_CFG_QM_SRF_17 0xF46CD4825 826#define mmTPC5_CFG_QM_SRF_18 0xF46CD8827 828#define mmTPC5_CFG_QM_SRF_19 0xF46CDC829 830#define mmTPC5_CFG_QM_SRF_20 0xF46CE0831 832#define mmTPC5_CFG_QM_SRF_21 0xF46CE4833 834#define mmTPC5_CFG_QM_SRF_22 0xF46CE8835 836#define mmTPC5_CFG_QM_SRF_23 0xF46CEC837 838#define mmTPC5_CFG_QM_SRF_24 0xF46CF0839 840#define mmTPC5_CFG_QM_SRF_25 0xF46CF4841 842#define mmTPC5_CFG_QM_SRF_26 0xF46CF8843 844#define mmTPC5_CFG_QM_SRF_27 0xF46CFC845 846#define mmTPC5_CFG_QM_SRF_28 0xF46D00847 848#define mmTPC5_CFG_QM_SRF_29 0xF46D04849 850#define mmTPC5_CFG_QM_SRF_30 0xF46D08851 852#define mmTPC5_CFG_QM_SRF_31 0xF46D0C853 854#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46D10855 856#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D14857 858#define mmTPC5_CFG_ARUSER 0xF46D18859 860#define mmTPC5_CFG_AWUSER 0xF46D1C861 862#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF46E00863 864#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF46E04865 866#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF46E08867 868#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF46E0C869 870#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF46E10871 872#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF46E14873 874#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF46E18875 876#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF46E1C877 878#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF46E20879 880#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF46E24881 882#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF46E28883 884#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF46E2C885 886#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */887