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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_14#define ASIC_REG_TPC5_CMDQ_REGS_H_15 16/*17 *****************************************18 * TPC5_CMDQ (Prototype: CMDQ)19 *****************************************20 */21 22#define mmTPC5_CMDQ_GLBL_CFG0 0xF4900023 24#define mmTPC5_CMDQ_GLBL_CFG1 0xF4900425 26#define mmTPC5_CMDQ_GLBL_PROT 0xF4900827 28#define mmTPC5_CMDQ_GLBL_ERR_CFG 0xF4900C29 30#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO 0xF4901031 32#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI 0xF4901433 34#define mmTPC5_CMDQ_GLBL_ERR_WDATA 0xF4901835 36#define mmTPC5_CMDQ_GLBL_SECURE_PROPS 0xF4901C37 38#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS 0xF4902039 40#define mmTPC5_CMDQ_GLBL_STS0 0xF4902441 42#define mmTPC5_CMDQ_GLBL_STS1 0xF4902843 44#define mmTPC5_CMDQ_CQ_CFG0 0xF490B045 46#define mmTPC5_CMDQ_CQ_CFG1 0xF490B447 48#define mmTPC5_CMDQ_CQ_ARUSER 0xF490B849 50#define mmTPC5_CMDQ_CQ_PTR_LO 0xF490C051 52#define mmTPC5_CMDQ_CQ_PTR_HI 0xF490C453 54#define mmTPC5_CMDQ_CQ_TSIZE 0xF490C855 56#define mmTPC5_CMDQ_CQ_CTL 0xF490CC57 58#define mmTPC5_CMDQ_CQ_PTR_LO_STS 0xF490D459 60#define mmTPC5_CMDQ_CQ_PTR_HI_STS 0xF490D861 62#define mmTPC5_CMDQ_CQ_TSIZE_STS 0xF490DC63 64#define mmTPC5_CMDQ_CQ_CTL_STS 0xF490E065 66#define mmTPC5_CMDQ_CQ_STS0 0xF490E467 68#define mmTPC5_CMDQ_CQ_STS1 0xF490E869 70#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN 0xF490F071 72#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF490F473 74#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT 0xF490F875 76#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF490FC77 78#define mmTPC5_CMDQ_CQ_IFIFO_CNT 0xF4910879 80#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF4912081 82#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF4912483 84#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF4912885 86#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF4912C87 88#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF4913089 90#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF4913491 92#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF4913893 94#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF4913C95 96#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF4914097 98#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF4914499 100#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF49148101 102#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF4914C103 104#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF49150105 106#define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF49154107 108#define mmTPC5_CMDQ_CP_FENCE0_RDATA 0xF49158109 110#define mmTPC5_CMDQ_CP_FENCE1_RDATA 0xF4915C111 112#define mmTPC5_CMDQ_CP_FENCE2_RDATA 0xF49160113 114#define mmTPC5_CMDQ_CP_FENCE3_RDATA 0xF49164115 116#define mmTPC5_CMDQ_CP_FENCE0_CNT 0xF49168117 118#define mmTPC5_CMDQ_CP_FENCE1_CNT 0xF4916C119 120#define mmTPC5_CMDQ_CP_FENCE2_CNT 0xF49170121 122#define mmTPC5_CMDQ_CP_FENCE3_CNT 0xF49174123 124#define mmTPC5_CMDQ_CP_STS 0xF49178125 126#define mmTPC5_CMDQ_CP_CURRENT_INST_LO 0xF4917C127 128#define mmTPC5_CMDQ_CP_CURRENT_INST_HI 0xF49180129 130#define mmTPC5_CMDQ_CP_BARRIER_CFG 0xF49184131 132#define mmTPC5_CMDQ_CP_DBG_0 0xF49188133 134#define mmTPC5_CMDQ_CQ_BUF_ADDR 0xF49308135 136#define mmTPC5_CMDQ_CQ_BUF_RDATA 0xF4930C137 138#endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */139