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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC5_QM_REGS_H_14#define ASIC_REG_TPC5_QM_REGS_H_15 16/*17 *****************************************18 * TPC5_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmTPC5_QM_GLBL_CFG0 0xF4800023 24#define mmTPC5_QM_GLBL_CFG1 0xF4800425 26#define mmTPC5_QM_GLBL_PROT 0xF4800827 28#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C29 30#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF4801031 32#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF4801433 34#define mmTPC5_QM_GLBL_ERR_WDATA 0xF4801835 36#define mmTPC5_QM_GLBL_SECURE_PROPS 0xF4801C37 38#define mmTPC5_QM_GLBL_NON_SECURE_PROPS 0xF4802039 40#define mmTPC5_QM_GLBL_STS0 0xF4802441 42#define mmTPC5_QM_GLBL_STS1 0xF4802843 44#define mmTPC5_QM_PQ_BASE_LO 0xF4806045 46#define mmTPC5_QM_PQ_BASE_HI 0xF4806447 48#define mmTPC5_QM_PQ_SIZE 0xF4806849 50#define mmTPC5_QM_PQ_PI 0xF4806C51 52#define mmTPC5_QM_PQ_CI 0xF4807053 54#define mmTPC5_QM_PQ_CFG0 0xF4807455 56#define mmTPC5_QM_PQ_CFG1 0xF4807857 58#define mmTPC5_QM_PQ_ARUSER 0xF4807C59 60#define mmTPC5_QM_PQ_PUSH0 0xF4808061 62#define mmTPC5_QM_PQ_PUSH1 0xF4808463 64#define mmTPC5_QM_PQ_PUSH2 0xF4808865 66#define mmTPC5_QM_PQ_PUSH3 0xF4808C67 68#define mmTPC5_QM_PQ_STS0 0xF4809069 70#define mmTPC5_QM_PQ_STS1 0xF4809471 72#define mmTPC5_QM_PQ_RD_RATE_LIM_EN 0xF480A073 74#define mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF480A475 76#define mmTPC5_QM_PQ_RD_RATE_LIM_SAT 0xF480A877 78#define mmTPC5_QM_PQ_RD_RATE_LIM_TOUT 0xF480AC79 80#define mmTPC5_QM_CQ_CFG0 0xF480B081 82#define mmTPC5_QM_CQ_CFG1 0xF480B483 84#define mmTPC5_QM_CQ_ARUSER 0xF480B885 86#define mmTPC5_QM_CQ_PTR_LO 0xF480C087 88#define mmTPC5_QM_CQ_PTR_HI 0xF480C489 90#define mmTPC5_QM_CQ_TSIZE 0xF480C891 92#define mmTPC5_QM_CQ_CTL 0xF480CC93 94#define mmTPC5_QM_CQ_PTR_LO_STS 0xF480D495 96#define mmTPC5_QM_CQ_PTR_HI_STS 0xF480D897 98#define mmTPC5_QM_CQ_TSIZE_STS 0xF480DC99 100#define mmTPC5_QM_CQ_CTL_STS 0xF480E0101 102#define mmTPC5_QM_CQ_STS0 0xF480E4103 104#define mmTPC5_QM_CQ_STS1 0xF480E8105 106#define mmTPC5_QM_CQ_RD_RATE_LIM_EN 0xF480F0107 108#define mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF480F4109 110#define mmTPC5_QM_CQ_RD_RATE_LIM_SAT 0xF480F8111 112#define mmTPC5_QM_CQ_RD_RATE_LIM_TOUT 0xF480FC113 114#define mmTPC5_QM_CQ_IFIFO_CNT 0xF48108115 116#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO 0xF48120117 118#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI 0xF48124119 120#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO 0xF48128121 122#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI 0xF4812C123 124#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO 0xF48130125 126#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI 0xF48134127 128#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO 0xF48138129 130#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI 0xF4813C131 132#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET 0xF48140133 134#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF48144135 136#define mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF48148137 138#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF4814C139 140#define mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF48150141 142#define mmTPC5_QM_CP_LDMA_COMMIT_OFFSET 0xF48154143 144#define mmTPC5_QM_CP_FENCE0_RDATA 0xF48158145 146#define mmTPC5_QM_CP_FENCE1_RDATA 0xF4815C147 148#define mmTPC5_QM_CP_FENCE2_RDATA 0xF48160149 150#define mmTPC5_QM_CP_FENCE3_RDATA 0xF48164151 152#define mmTPC5_QM_CP_FENCE0_CNT 0xF48168153 154#define mmTPC5_QM_CP_FENCE1_CNT 0xF4816C155 156#define mmTPC5_QM_CP_FENCE2_CNT 0xF48170157 158#define mmTPC5_QM_CP_FENCE3_CNT 0xF48174159 160#define mmTPC5_QM_CP_STS 0xF48178161 162#define mmTPC5_QM_CP_CURRENT_INST_LO 0xF4817C163 164#define mmTPC5_QM_CP_CURRENT_INST_HI 0xF48180165 166#define mmTPC5_QM_CP_BARRIER_CFG 0xF48184167 168#define mmTPC5_QM_CP_DBG_0 0xF48188169 170#define mmTPC5_QM_PQ_BUF_ADDR 0xF48300171 172#define mmTPC5_QM_PQ_BUF_RDATA 0xF48304173 174#define mmTPC5_QM_CQ_BUF_ADDR 0xF48308175 176#define mmTPC5_QM_CQ_BUF_RDATA 0xF4830C177 178#endif /* ASIC_REG_TPC5_QM_REGS_H_ */179