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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC6_CFG_REGS_H_14#define ASIC_REG_TPC6_CFG_REGS_H_15 16/*17 *****************************************18 * TPC6_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF8640023 24#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF8640425 26#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF8640827 28#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C29 30#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF8641031 32#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF8641433 34#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF8641835 36#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C37 38#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8642039 40#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF8642441 42#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF8642843 44#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C45 46#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF8643047 48#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF8643449 50#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8643851 52#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C53 54#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF8644055 56#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF8644457 58#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF8644859 60#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C61 62#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8645063 64#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF8645465 66#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF8645867 68#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C69 70#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8646071 72#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF8646473 74#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF8646875 76#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C77 78#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF8647079 80#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF8647481 82#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8647883 84#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C85 86#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF8648087 88#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF8648489 90#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF8648891 92#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C93 94#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8649095 96#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF8649497 98#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF8649899 100#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C101 102#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0103 104#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4105 106#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8107 108#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC109 110#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0111 112#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4113 114#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8115 116#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC117 118#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0119 120#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4121 122#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8123 124#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC125 126#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0127 128#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4129 130#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8131 132#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC133 134#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0135 136#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4137 138#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8139 140#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC141 142#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0143 144#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4145 146#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8147 148#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC149 150#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500151 152#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504153 154#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508155 156#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C157 158#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510159 160#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514161 162#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518163 164#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C165 166#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520167 168#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524169 170#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528171 172#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C173 174#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530175 176#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534177 178#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538179 180#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C181 182#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540183 184#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544185 186#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548187 188#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C189 190#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550191 192#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554193 194#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558195 196#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C197 198#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560199 200#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564201 202#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568203 204#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C205 206#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570207 208#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574209 210#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578211 212#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C213 214#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580215 216#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584217 218#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588219 220#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C221 222#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590223 224#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594225 226#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598227 228#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C229 230#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0231 232#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4233 234#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8235 236#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC237 238#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0239 240#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4241 242#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8243 244#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC245 246#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0247 248#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4249 250#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8251 252#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC253 254#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0255 256#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4257 258#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8259 260#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC261 262#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0263 264#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4265 266#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8267 268#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC269 270#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0271 272#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4273 274#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8275 276#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC277 278#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600279 280#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604281 282#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608283 284#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C285 286#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610287 288#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614289 290#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618291 292#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C293 294#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620295 296#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624297 298#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628299 300#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C301 302#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630303 304#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634305 306#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638307 308#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C309 310#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640311 312#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644313 314#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648315 316#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C317 318#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650319 320#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654321 322#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658323 324#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C325 326#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660327 328#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664329 330#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668331 332#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C333 334#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670335 336#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674337 338#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678339 340#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C341 342#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680343 344#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684345 346#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688347 348#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C349 350#define mmTPC6_CFG_KERNEL_SRF_0 0xF86690351 352#define mmTPC6_CFG_KERNEL_SRF_1 0xF86694353 354#define mmTPC6_CFG_KERNEL_SRF_2 0xF86698355 356#define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C357 358#define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0359 360#define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4361 362#define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8363 364#define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC365 366#define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0367 368#define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4369 370#define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8371 372#define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC373 374#define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0375 376#define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4377 378#define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8379 380#define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC381 382#define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0383 384#define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4385 386#define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8387 388#define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC389 390#define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0391 392#define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4393 394#define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8395 396#define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC397 398#define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0399 400#define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4401 402#define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8403 404#define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC405 406#define mmTPC6_CFG_KERNEL_SRF_28 0xF86700407 408#define mmTPC6_CFG_KERNEL_SRF_29 0xF86704409 410#define mmTPC6_CFG_KERNEL_SRF_30 0xF86708411 412#define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C413 414#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710415 416#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714417 418#define mmTPC6_CFG_RESERVED_DESC_END 0xF86738419 420#define mmTPC6_CFG_ROUND_CSR 0xF867FC421 422#define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800423 424#define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804425 426#define mmTPC6_CFG_SEMAPHORE 0xF86808427 428#define mmTPC6_CFG_VFLAGS 0xF8680C429 430#define mmTPC6_CFG_SFLAGS 0xF86810431 432#define mmTPC6_CFG_LFSR_POLYNOM 0xF86818433 434#define mmTPC6_CFG_STATUS 0xF8681C435 436#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820437 438#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824439 440#define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828441 442#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C443 444#define mmTPC6_CFG_TPC_CMD 0xF86830445 446#define mmTPC6_CFG_TPC_EXECUTE 0xF86838447 448#define mmTPC6_CFG_TPC_STALL 0xF8683C449 450#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840451 452#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844453 454#define mmTPC6_CFG_MSS_CONFIG 0xF86854455 456#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858457 458#define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C459 460#define mmTPC6_CFG_TSB_CONFIG 0xF86860461 462#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00463 464#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04465 466#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08467 468#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C469 470#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10471 472#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14473 474#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18475 476#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C477 478#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20479 480#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24481 482#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28483 484#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C485 486#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30487 488#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34489 490#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38491 492#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C493 494#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40495 496#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44497 498#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48499 500#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C501 502#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50503 504#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54505 506#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58507 508#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C509 510#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60511 512#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64513 514#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68515 516#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C517 518#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70519 520#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74521 522#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78523 524#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C525 526#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80527 528#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84529 530#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88531 532#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C533 534#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90535 536#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94537 538#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98539 540#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C541 542#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0543 544#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4545 546#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8547 548#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC549 550#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0551 552#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4553 554#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8555 556#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC557 558#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0559 560#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4561 562#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8563 564#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC565 566#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0567 568#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4569 570#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8571 572#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC573 574#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0575 576#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4577 578#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8579 580#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC581 582#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0583 584#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4585 586#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8587 588#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC589 590#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00591 592#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04593 594#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08595 596#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C597 598#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10599 600#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14601 602#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18603 604#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C605 606#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20607 608#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24609 610#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28611 612#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C613 614#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30615 616#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34617 618#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38619 620#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C621 622#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40623 624#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44625 626#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48627 628#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C629 630#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50631 632#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54633 634#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58635 636#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C637 638#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60639 640#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64641 642#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68643 644#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C645 646#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70647 648#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74649 650#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78651 652#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C653 654#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80655 656#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84657 658#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88659 660#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C661 662#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90663 664#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94665 666#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98667 668#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C669 670#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0671 672#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4673 674#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8675 676#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC677 678#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0679 680#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4681 682#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8683 684#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC685 686#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0687 688#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4689 690#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8691 692#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC693 694#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0695 696#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4697 698#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8699 700#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC701 702#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0703 704#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4705 706#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8707 708#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC709 710#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0711 712#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4713 714#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8715 716#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC717 718#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00719 720#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04721 722#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08723 724#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C725 726#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10727 728#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14729 730#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18731 732#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C733 734#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20735 736#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24737 738#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28739 740#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C741 742#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30743 744#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34745 746#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38747 748#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C749 750#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40751 752#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44753 754#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48755 756#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C757 758#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50759 760#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54761 762#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58763 764#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C765 766#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60767 768#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64769 770#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68771 772#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C773 774#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70775 776#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74777 778#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78779 780#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C781 782#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80783 784#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84785 786#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88787 788#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C789 790#define mmTPC6_CFG_QM_SRF_0 0xF86C90791 792#define mmTPC6_CFG_QM_SRF_1 0xF86C94793 794#define mmTPC6_CFG_QM_SRF_2 0xF86C98795 796#define mmTPC6_CFG_QM_SRF_3 0xF86C9C797 798#define mmTPC6_CFG_QM_SRF_4 0xF86CA0799 800#define mmTPC6_CFG_QM_SRF_5 0xF86CA4801 802#define mmTPC6_CFG_QM_SRF_6 0xF86CA8803 804#define mmTPC6_CFG_QM_SRF_7 0xF86CAC805 806#define mmTPC6_CFG_QM_SRF_8 0xF86CB0807 808#define mmTPC6_CFG_QM_SRF_9 0xF86CB4809 810#define mmTPC6_CFG_QM_SRF_10 0xF86CB8811 812#define mmTPC6_CFG_QM_SRF_11 0xF86CBC813 814#define mmTPC6_CFG_QM_SRF_12 0xF86CC0815 816#define mmTPC6_CFG_QM_SRF_13 0xF86CC4817 818#define mmTPC6_CFG_QM_SRF_14 0xF86CC8819 820#define mmTPC6_CFG_QM_SRF_15 0xF86CCC821 822#define mmTPC6_CFG_QM_SRF_16 0xF86CD0823 824#define mmTPC6_CFG_QM_SRF_17 0xF86CD4825 826#define mmTPC6_CFG_QM_SRF_18 0xF86CD8827 828#define mmTPC6_CFG_QM_SRF_19 0xF86CDC829 830#define mmTPC6_CFG_QM_SRF_20 0xF86CE0831 832#define mmTPC6_CFG_QM_SRF_21 0xF86CE4833 834#define mmTPC6_CFG_QM_SRF_22 0xF86CE8835 836#define mmTPC6_CFG_QM_SRF_23 0xF86CEC837 838#define mmTPC6_CFG_QM_SRF_24 0xF86CF0839 840#define mmTPC6_CFG_QM_SRF_25 0xF86CF4841 842#define mmTPC6_CFG_QM_SRF_26 0xF86CF8843 844#define mmTPC6_CFG_QM_SRF_27 0xF86CFC845 846#define mmTPC6_CFG_QM_SRF_28 0xF86D00847 848#define mmTPC6_CFG_QM_SRF_29 0xF86D04849 850#define mmTPC6_CFG_QM_SRF_30 0xF86D08851 852#define mmTPC6_CFG_QM_SRF_31 0xF86D0C853 854#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10855 856#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14857 858#define mmTPC6_CFG_ARUSER 0xF86D18859 860#define mmTPC6_CFG_AWUSER 0xF86D1C861 862#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00863 864#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04865 866#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08867 868#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C869 870#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10871 872#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14873 874#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18875 876#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C877 878#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20879 880#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24881 882#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28883 884#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C885 886#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */887