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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC7_CFG_REGS_H_14#define ASIC_REG_TPC7_CFG_REGS_H_15 16/*17 *****************************************18 * TPC7_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC640023 24#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC640425 26#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC640827 28#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C29 30#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC641031 32#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC641433 34#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xFC641835 36#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC641C37 38#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC642039 40#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xFC642441 42#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC642843 44#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC642C45 46#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xFC643047 48#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC643449 50#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC643851 52#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xFC643C53 54#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC644055 56#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC644457 58#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xFC644859 60#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC644C61 62#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC645063 64#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC645465 66#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC645867 68#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC645C69 70#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC646071 72#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xFC646473 74#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC646875 76#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC646C77 78#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xFC647079 80#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC647481 82#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC647883 84#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xFC647C85 86#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC648087 88#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC648489 90#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xFC648891 92#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC648C93 94#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC649095 96#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xFC649497 98#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC649899 100#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC649C101 102#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC64A0103 104#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC64A4105 106#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC64A8107 108#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC64AC109 110#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xFC64B0111 112#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC64B4113 114#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC64B8115 116#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xFC64BC117 118#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC64C0119 120#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC64C4121 122#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xFC64C8123 124#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC64CC125 126#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC64D0127 128#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xFC64D4129 130#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64D8131 132#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64DC133 134#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xFC64E0135 136#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64E4137 138#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64E8139 140#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64EC141 142#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64F0143 144#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64F4145 146#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64F8147 148#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xFC64FC149 150#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC6500151 152#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC6504153 154#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6508155 156#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC650C157 158#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC6510159 160#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6514161 162#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC6518163 164#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC651C165 166#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6520167 168#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC6524169 170#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC6528171 172#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xFC652C173 174#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC6530175 176#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC6534177 178#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC6538179 180#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC653C181 182#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC6540183 184#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC6544185 186#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6548187 188#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC654C189 190#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC6550191 192#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6554193 194#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6558195 196#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC655C197 198#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6560199 200#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6564201 202#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC6568203 204#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xFC656C205 206#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6570207 208#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6574209 210#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6578211 212#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC657C213 214#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC6580215 216#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6584217 218#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6588219 220#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC658C221 222#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC6590223 224#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6594225 226#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6598227 228#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC659C229 230#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xFC65A0231 232#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC65A4233 234#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC65A8235 236#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xFC65AC237 238#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC65B0239 240#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC65B4241 242#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xFC65B8243 244#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC65BC245 246#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC65C0247 248#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xFC65C4249 250#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC65C8251 252#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC65CC253 254#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC65D0255 256#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC65D4257 258#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC65D8259 260#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC65DC261 262#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xFC65E0263 264#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC65E4265 266#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC65E8267 268#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xFC65EC269 270#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC65F0271 272#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC65F4273 274#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xFC65F8275 276#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC65FC277 278#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC6600279 280#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6604281 282#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6608283 284#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC660C285 286#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6610287 288#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6614289 290#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC6618291 292#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC661C293 294#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6620295 296#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6624297 298#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC6628299 300#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xFC662C301 302#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC6630303 304#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC6634305 306#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6638307 308#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC663C309 310#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC6640311 312#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6644313 314#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC6648315 316#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC664C317 318#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6650319 320#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC6654321 322#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC6658323 324#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xFC665C325 326#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6660327 328#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC6664329 330#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6668331 332#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC666C333 334#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6670335 336#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC6674337 338#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC6678339 340#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC667C341 342#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC6680343 344#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC6684345 346#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC6688347 348#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC668C349 350#define mmTPC7_CFG_KERNEL_SRF_0 0xFC6690351 352#define mmTPC7_CFG_KERNEL_SRF_1 0xFC6694353 354#define mmTPC7_CFG_KERNEL_SRF_2 0xFC6698355 356#define mmTPC7_CFG_KERNEL_SRF_3 0xFC669C357 358#define mmTPC7_CFG_KERNEL_SRF_4 0xFC66A0359 360#define mmTPC7_CFG_KERNEL_SRF_5 0xFC66A4361 362#define mmTPC7_CFG_KERNEL_SRF_6 0xFC66A8363 364#define mmTPC7_CFG_KERNEL_SRF_7 0xFC66AC365 366#define mmTPC7_CFG_KERNEL_SRF_8 0xFC66B0367 368#define mmTPC7_CFG_KERNEL_SRF_9 0xFC66B4369 370#define mmTPC7_CFG_KERNEL_SRF_10 0xFC66B8371 372#define mmTPC7_CFG_KERNEL_SRF_11 0xFC66BC373 374#define mmTPC7_CFG_KERNEL_SRF_12 0xFC66C0375 376#define mmTPC7_CFG_KERNEL_SRF_13 0xFC66C4377 378#define mmTPC7_CFG_KERNEL_SRF_14 0xFC66C8379 380#define mmTPC7_CFG_KERNEL_SRF_15 0xFC66CC381 382#define mmTPC7_CFG_KERNEL_SRF_16 0xFC66D0383 384#define mmTPC7_CFG_KERNEL_SRF_17 0xFC66D4385 386#define mmTPC7_CFG_KERNEL_SRF_18 0xFC66D8387 388#define mmTPC7_CFG_KERNEL_SRF_19 0xFC66DC389 390#define mmTPC7_CFG_KERNEL_SRF_20 0xFC66E0391 392#define mmTPC7_CFG_KERNEL_SRF_21 0xFC66E4393 394#define mmTPC7_CFG_KERNEL_SRF_22 0xFC66E8395 396#define mmTPC7_CFG_KERNEL_SRF_23 0xFC66EC397 398#define mmTPC7_CFG_KERNEL_SRF_24 0xFC66F0399 400#define mmTPC7_CFG_KERNEL_SRF_25 0xFC66F4401 402#define mmTPC7_CFG_KERNEL_SRF_26 0xFC66F8403 404#define mmTPC7_CFG_KERNEL_SRF_27 0xFC66FC405 406#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6700407 408#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6704409 410#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6708411 412#define mmTPC7_CFG_KERNEL_SRF_31 0xFC670C413 414#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC6710415 416#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6714417 418#define mmTPC7_CFG_RESERVED_DESC_END 0xFC6738419 420#define mmTPC7_CFG_ROUND_CSR 0xFC67FC421 422#define mmTPC7_CFG_TBUF_BASE_ADDR_LOW 0xFC6800423 424#define mmTPC7_CFG_TBUF_BASE_ADDR_HIGH 0xFC6804425 426#define mmTPC7_CFG_SEMAPHORE 0xFC6808427 428#define mmTPC7_CFG_VFLAGS 0xFC680C429 430#define mmTPC7_CFG_SFLAGS 0xFC6810431 432#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6818433 434#define mmTPC7_CFG_STATUS 0xFC681C435 436#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6820437 438#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6824439 440#define mmTPC7_CFG_SM_BASE_ADDRESS_LOW 0xFC6828441 442#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC682C443 444#define mmTPC7_CFG_TPC_CMD 0xFC6830445 446#define mmTPC7_CFG_TPC_EXECUTE 0xFC6838447 448#define mmTPC7_CFG_TPC_STALL 0xFC683C449 450#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6840451 452#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6844453 454#define mmTPC7_CFG_MSS_CONFIG 0xFC6854455 456#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6858457 458#define mmTPC7_CFG_TPC_INTR_MASK 0xFC685C459 460#define mmTPC7_CFG_TSB_CONFIG 0xFC6860461 462#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00463 464#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04465 466#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08467 468#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C469 470#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10471 472#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14473 474#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6A18475 476#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A1C477 478#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A20479 480#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6A24481 482#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A28483 484#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A2C485 486#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6A30487 488#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A34489 490#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A38491 492#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xFC6A3C493 494#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A40495 496#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A44497 498#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6A48499 500#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A4C501 502#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A50503 504#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A54505 506#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A58507 508#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A5C509 510#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A60511 512#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6A64513 514#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A68515 516#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A6C517 518#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6A70519 520#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A74521 522#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A78523 524#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xFC6A7C525 526#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A80527 528#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A84529 530#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6A88531 532#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A8C533 534#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A90535 536#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6A94537 538#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A98539 540#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A9C541 542#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6AA0543 544#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6AA4545 546#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6AA8547 548#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6AAC549 550#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xFC6AB0551 552#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6AB4553 554#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6AB8555 556#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xFC6ABC557 558#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6AC0559 560#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6AC4561 562#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xFC6AC8563 564#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6ACC565 566#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6AD0567 568#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xFC6AD4569 570#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AD8571 572#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6ADC573 574#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xFC6AE0575 576#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AE4577 578#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AE8579 580#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AEC581 582#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AF0583 584#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AF4585 586#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6AF8587 588#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xFC6AFC589 590#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6B00591 592#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6B04593 594#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6B08595 596#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6B0C597 598#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6B10599 600#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6B14601 602#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6B18603 604#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6B1C605 606#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6B20607 608#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6B24609 610#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6B28611 612#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xFC6B2C613 614#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6B30615 616#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6B34617 618#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6B38619 620#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6B3C621 622#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6B40623 624#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6B44625 626#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6B48627 628#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6B4C629 630#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6B50631 632#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6B54633 634#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B58635 636#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B5C637 638#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6B60639 640#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B64641 642#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B68643 644#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xFC6B6C645 646#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B70647 648#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B74649 650#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6B78651 652#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B7C653 654#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B80655 656#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B84657 658#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B88659 660#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B8C661 662#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B90663 664#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6B94665 666#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B98667 668#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B9C669 670#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xFC6BA0671 672#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6BA4673 674#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6BA8675 676#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xFC6BAC677 678#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6BB0679 680#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6BB4681 682#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xFC6BB8683 684#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6BBC685 686#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6BC0687 688#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xFC6BC4689 690#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6BC8691 692#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6BCC693 694#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6BD0695 696#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6BD4697 698#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6BD8699 700#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6BDC701 702#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xFC6BE0703 704#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6BE4705 706#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6BE8707 708#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xFC6BEC709 710#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6BF0711 712#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6BF4713 714#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xFC6BF8715 716#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6BFC717 718#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6C00719 720#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6C04721 722#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6C08723 724#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6C0C725 726#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6C10727 728#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6C14729 730#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6C18731 732#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6C1C733 734#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6C20735 736#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6C24737 738#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6C28739 740#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xFC6C2C741 742#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6C30743 744#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6C34745 746#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6C38747 748#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6C3C749 750#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6C40751 752#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6C44753 754#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6C48755 756#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6C4C757 758#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6C50759 760#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6C54761 762#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6C58763 764#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xFC6C5C765 766#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6C60767 768#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6C64769 770#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6C68771 772#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6C6C773 774#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6C70775 776#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6C74777 778#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6C78779 780#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6C7C781 782#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6C80783 784#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6C84785 786#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6C88787 788#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6C8C789 790#define mmTPC7_CFG_QM_SRF_0 0xFC6C90791 792#define mmTPC7_CFG_QM_SRF_1 0xFC6C94793 794#define mmTPC7_CFG_QM_SRF_2 0xFC6C98795 796#define mmTPC7_CFG_QM_SRF_3 0xFC6C9C797 798#define mmTPC7_CFG_QM_SRF_4 0xFC6CA0799 800#define mmTPC7_CFG_QM_SRF_5 0xFC6CA4801 802#define mmTPC7_CFG_QM_SRF_6 0xFC6CA8803 804#define mmTPC7_CFG_QM_SRF_7 0xFC6CAC805 806#define mmTPC7_CFG_QM_SRF_8 0xFC6CB0807 808#define mmTPC7_CFG_QM_SRF_9 0xFC6CB4809 810#define mmTPC7_CFG_QM_SRF_10 0xFC6CB8811 812#define mmTPC7_CFG_QM_SRF_11 0xFC6CBC813 814#define mmTPC7_CFG_QM_SRF_12 0xFC6CC0815 816#define mmTPC7_CFG_QM_SRF_13 0xFC6CC4817 818#define mmTPC7_CFG_QM_SRF_14 0xFC6CC8819 820#define mmTPC7_CFG_QM_SRF_15 0xFC6CCC821 822#define mmTPC7_CFG_QM_SRF_16 0xFC6CD0823 824#define mmTPC7_CFG_QM_SRF_17 0xFC6CD4825 826#define mmTPC7_CFG_QM_SRF_18 0xFC6CD8827 828#define mmTPC7_CFG_QM_SRF_19 0xFC6CDC829 830#define mmTPC7_CFG_QM_SRF_20 0xFC6CE0831 832#define mmTPC7_CFG_QM_SRF_21 0xFC6CE4833 834#define mmTPC7_CFG_QM_SRF_22 0xFC6CE8835 836#define mmTPC7_CFG_QM_SRF_23 0xFC6CEC837 838#define mmTPC7_CFG_QM_SRF_24 0xFC6CF0839 840#define mmTPC7_CFG_QM_SRF_25 0xFC6CF4841 842#define mmTPC7_CFG_QM_SRF_26 0xFC6CF8843 844#define mmTPC7_CFG_QM_SRF_27 0xFC6CFC845 846#define mmTPC7_CFG_QM_SRF_28 0xFC6D00847 848#define mmTPC7_CFG_QM_SRF_29 0xFC6D04849 850#define mmTPC7_CFG_QM_SRF_30 0xFC6D08851 852#define mmTPC7_CFG_QM_SRF_31 0xFC6D0C853 854#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6D10855 856#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D14857 858#define mmTPC7_CFG_ARUSER 0xFC6D18859 860#define mmTPC7_CFG_AWUSER 0xFC6D1C861 862#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC6E00863 864#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC6E04865 866#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC6E08867 868#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC6E0C869 870#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC6E10871 872#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC6E14873 874#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC6E18875 876#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC6E1C877 878#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC6E20879 880#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC6E24881 882#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC6E28883 884#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC6E2C885 886#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */887