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1// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \2// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type -fnative-int16-type \3// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \4// RUN: --check-prefixes=CHECK,NATIVE_HALF \5// RUN: -DTARGET=dx -DFNATTRS="hidden noundef"6// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \7// RUN: dxil-pc-shadermodel6.3-library %s -emit-llvm -disable-llvm-passes \8// RUN: -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \9// RUN: -DTARGET=dx -DFNATTRS="hidden noundef"10// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \11// RUN: spirv-unknown-vulkan-compute %s -fnative-half-type -fnative-int16-type \12// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \13// RUN: --check-prefixes=CHECK,NATIVE_HALF \14// RUN: -DTARGET=spv -DFNATTRS="hidden spir_func noundef"15// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \16// RUN: spirv-unknown-vulkan-compute %s -emit-llvm -disable-llvm-passes \17// RUN: -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \18// RUN: -DTARGET=spv -DFNATTRS="hidden spir_func noundef"19 20// NATIVE_HALF: define [[FNATTRS]] i32 @21// NATIVE_HALF: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.f16(22// NATIVE_HALF: ret i32 %hlsl.sign23// NO_HALF: define [[FNATTRS]] i32 @24// NO_HALF: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.f32(25// NO_HALF: ret i32 %hlsl.sign26int test_sign_half(half p0) { return sign(p0); }27 28// NATIVE_HALF: define [[FNATTRS]] <2 x i32> @29// NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2f16(30// NATIVE_HALF: ret <2 x i32> %hlsl.sign31// NO_HALF: define [[FNATTRS]] <2 x i32> @32// NO_HALF: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2f32(33// NO_HALF: ret <2 x i32> %hlsl.sign34int2 test_sign_half2(half2 p0) { return sign(p0); }35 36// NATIVE_HALF: define [[FNATTRS]] <3 x i32> @37// NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3f16(38// NATIVE_HALF: ret <3 x i32> %hlsl.sign39// NO_HALF: define [[FNATTRS]] <3 x i32> @40// NO_HALF: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3f32(41// NO_HALF: ret <3 x i32> %hlsl.sign42int3 test_sign_half3(half3 p0) { return sign(p0); }43 44// NATIVE_HALF: define [[FNATTRS]] <4 x i32> @45// NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4f16(46// NATIVE_HALF: ret <4 x i32> %hlsl.sign47// NO_HALF: define [[FNATTRS]] <4 x i32> @48// NO_HALF: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4f32(49// NO_HALF: ret <4 x i32> %hlsl.sign50int4 test_sign_half4(half4 p0) { return sign(p0); }51 52 53// CHECK: define [[FNATTRS]] i32 @54// CHECK: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.f32(55// CHECK: ret i32 %hlsl.sign56int test_sign_float(float p0) { return sign(p0); }57 58// CHECK: define [[FNATTRS]] <2 x i32> @59// CHECK: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2f32(60// CHECK: ret <2 x i32> %hlsl.sign61int2 test_sign_float2(float2 p0) { return sign(p0); }62 63// CHECK: define [[FNATTRS]] <3 x i32> @64// CHECK: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3f32(65// CHECK: ret <3 x i32> %hlsl.sign66int3 test_sign_float3(float3 p0) { return sign(p0); }67 68// CHECK: define [[FNATTRS]] <4 x i32> @69// CHECK: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4f32(70// CHECK: ret <4 x i32> %hlsl.sign71int4 test_sign_float4(float4 p0) { return sign(p0); }72 73 74// CHECK: define [[FNATTRS]] i32 @75// CHECK: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.f64(76// CHECK: ret i32 %hlsl.sign77int test_sign_double(double p0) { return sign(p0); }78 79// CHECK: define [[FNATTRS]] <2 x i32> @80// CHECK: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2f64(81// CHECK: ret <2 x i32> %hlsl.sign82int2 test_sign_double2(double2 p0) { return sign(p0); }83 84// CHECK: define [[FNATTRS]] <3 x i32> @85// CHECK: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3f64(86// CHECK: ret <3 x i32> %hlsl.sign87int3 test_sign_double3(double3 p0) { return sign(p0); }88 89// CHECK: define [[FNATTRS]] <4 x i32> @90// CHECK: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4f64(91// CHECK: ret <4 x i32> %hlsl.sign92int4 test_sign_double4(double4 p0) { return sign(p0); }93 94 95#ifdef __HLSL_ENABLE_16_BIT96// NATIVE_HALF: define [[FNATTRS]] i32 @97// NATIVE_HALF: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.i16(98// NATIVE_HALF: ret i32 %hlsl.sign99int test_sign_int16_t(int16_t p0) { return sign(p0); }100 101// NATIVE_HALF: define [[FNATTRS]] <2 x i32> @102// NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2i16(103// NATIVE_HALF: ret <2 x i32> %hlsl.sign104int2 test_sign_int16_t2(int16_t2 p0) { return sign(p0); }105 106// NATIVE_HALF: define [[FNATTRS]] <3 x i32> @107// NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3i16(108// NATIVE_HALF: ret <3 x i32> %hlsl.sign109int3 test_sign_int16_t3(int16_t3 p0) { return sign(p0); }110 111// NATIVE_HALF: define [[FNATTRS]] <4 x i32> @112// NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4i16(113// NATIVE_HALF: ret <4 x i32> %hlsl.sign114int4 test_sign_int16_t4(int16_t4 p0) { return sign(p0); }115 116 117// NATIVE_HALF: define [[FNATTRS]] i32 @118// NATIVE_HALF: [[CMP:%.*]] = icmp eq i16 [[ARG:%.*]], 0119// NATIVE_HALF: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1120int test_sign_uint16_t(uint16_t p0) { return sign(p0); }121 122// NATIVE_HALF: define [[FNATTRS]] <2 x i32> @123// NATIVE_HALF: [[CMP:%.*]] = icmp eq <2 x i16> [[ARG:%.*]], zeroinitializer124// NATIVE_HALF: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> splat (i32 1)125int2 test_sign_uint16_t2(uint16_t2 p0) { return sign(p0); }126 127// NATIVE_HALF: define [[FNATTRS]] <3 x i32> @128// NATIVE_HALF: [[CMP:%.*]] = icmp eq <3 x i16> [[ARG:%.*]], zeroinitializer129// NATIVE_HALF: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> splat (i32 1)130int3 test_sign_uint16_t3(uint16_t3 p0) { return sign(p0); }131 132// NATIVE_HALF: define [[FNATTRS]] <4 x i32> @133// NATIVE_HALF: [[CMP:%.*]] = icmp eq <4 x i16> [[ARG:%.*]], zeroinitializer134// NATIVE_HALF: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 1)135int4 test_sign_uint16_t4(uint16_t4 p0) { return sign(p0); }136#endif // __HLSL_ENABLE_16_BIT137 138 139// CHECK: define [[FNATTRS]] i32 @140// CHECK: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.i32(141// CHECK: ret i32 %hlsl.sign142int test_sign_int(int p0) { return sign(p0); }143 144// CHECK: define [[FNATTRS]] <2 x i32> @145// CHECK: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2i32(146// CHECK: ret <2 x i32> %hlsl.sign147int2 test_sign_int2(int2 p0) { return sign(p0); }148 149// CHECK: define [[FNATTRS]] <3 x i32> @150// CHECK: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3i32(151// CHECK: ret <3 x i32> %hlsl.sign152int3 test_sign_int3(int3 p0) { return sign(p0); }153 154// CHECK: define [[FNATTRS]] <4 x i32> @155// CHECK: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4i32(156// CHECK: ret <4 x i32> %hlsl.sign157int4 test_sign_int4(int4 p0) { return sign(p0); }158 159 160// CHECK: define [[FNATTRS]] i32 @161// CHECK: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0162// CHECK: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1163int test_sign_uint(uint p0) { return sign(p0); }164 165// CHECK: define [[FNATTRS]] <2 x i32> @166// CHECK: [[CMP:%.*]] = icmp eq <2 x i32> [[ARG:%.*]], zeroinitializer167// CHECK: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> splat (i32 1)168int2 test_sign_uint2(uint2 p0) { return sign(p0); }169 170// CHECK: define [[FNATTRS]] <3 x i32> @171// CHECK: [[CMP:%.*]] = icmp eq <3 x i32> [[ARG:%.*]], zeroinitializer172// CHECK: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> splat (i32 1)173int3 test_sign_uint3(uint3 p0) { return sign(p0); }174 175// CHECK: define [[FNATTRS]] <4 x i32> @176// CHECK: [[CMP:%.*]] = icmp eq <4 x i32> [[ARG:%.*]], zeroinitializer177// CHECK: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 1)178int4 test_sign_uint4(uint4 p0) { return sign(p0); }179 180 181// CHECK: define [[FNATTRS]] i32 @182// CHECK: %hlsl.sign = call i32 @llvm.[[TARGET]].sign.i64(183// CHECK: ret i32 %hlsl.sign184int test_sign_int64_t(int64_t p0) { return sign(p0); }185 186// CHECK: define [[FNATTRS]] <2 x i32> @187// CHECK: %hlsl.sign = call <2 x i32> @llvm.[[TARGET]].sign.v2i64(188// CHECK: ret <2 x i32> %hlsl.sign189int2 test_sign_int64_t2(int64_t2 p0) { return sign(p0); }190 191// CHECK: define [[FNATTRS]] <3 x i32> @192// CHECK: %hlsl.sign = call <3 x i32> @llvm.[[TARGET]].sign.v3i64(193// CHECK: ret <3 x i32> %hlsl.sign194int3 test_sign_int64_t3(int64_t3 p0) { return sign(p0); }195 196// CHECK: define [[FNATTRS]] <4 x i32> @197// CHECK: %hlsl.sign = call <4 x i32> @llvm.[[TARGET]].sign.v4i64(198// CHECK: ret <4 x i32> %hlsl.sign199int4 test_sign_int64_t4(int64_t4 p0) { return sign(p0); }200 201 202// CHECK: define [[FNATTRS]] i32 @203// CHECK: [[CMP:%.*]] = icmp eq i64 [[ARG:%.*]], 0204// CHECK: %hlsl.sign = select i1 [[CMP]], i32 0, i32 1205int test_sign_uint64_t(uint64_t p0) { return sign(p0); }206 207// CHECK: define [[FNATTRS]] <2 x i32> @208// CHECK: [[CMP:%.*]] = icmp eq <2 x i64> [[ARG:%.*]], zeroinitializer209// CHECK: %hlsl.sign = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> splat (i32 1)210int2 test_sign_uint64_t2(uint64_t2 p0) { return sign(p0); }211 212// CHECK: define [[FNATTRS]] <3 x i32> @213// CHECK: [[CMP:%.*]] = icmp eq <3 x i64> [[ARG:%.*]], zeroinitializer214// CHECK: %hlsl.sign = select <3 x i1> [[CMP]], <3 x i32> zeroinitializer, <3 x i32> splat (i32 1)215int3 test_sign_uint64_t3(uint64_t3 p0) { return sign(p0); }216 217// CHECK: define [[FNATTRS]] <4 x i32> @218// CHECK: [[CMP:%.*]] = icmp eq <4 x i64> [[ARG:%.*]], zeroinitializer219// CHECK: %hlsl.sign = select <4 x i1> [[CMP]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 1)220int4 test_sign_uint64_t4(uint64_t4 p0) { return sign(p0); }221