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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -mattr=+v8.2a,+fullfp16 | FileCheck %s3 4declare <4 x half> @llvm.nearbyint.v4f16(<4 x half>)5declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)6declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)7declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)8declare <4 x i16> @llvm.aarch64.neon.fcvtzs.v4i16.v4f16(<4 x half>)9declare <4 x i16> @llvm.aarch64.neon.fcvtzu.v4i16.v4f16(<4 x half>)10declare <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half>)11declare <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half>)12declare <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half>)13declare <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half>)14declare <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half>)15declare <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half>)16declare <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half>)17declare <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half>)18 19define dso_local <4 x half> @t_vrndi_f16(<4 x half> %a) {20; CHECK-LABEL: t_vrndi_f16:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: frinti v0.4h, v0.4h23; CHECK-NEXT: ret24entry:25 %vrndi1.i = tail call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)26 ret <4 x half> %vrndi1.i27}28 29define dso_local <8 x half> @t_vrndiq_f16(<8 x half> %a) {30; CHECK-LABEL: t_vrndiq_f16:31; CHECK: // %bb.0: // %entry32; CHECK-NEXT: frinti v0.8h, v0.8h33; CHECK-NEXT: ret34entry:35 %vrndi1.i = tail call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)36 ret <8 x half> %vrndi1.i37}38 39define dso_local <4 x half> @t_vsqrt_f16(<4 x half> %a) {40; CHECK-LABEL: t_vsqrt_f16:41; CHECK: // %bb.0: // %entry42; CHECK-NEXT: fsqrt v0.4h, v0.4h43; CHECK-NEXT: ret44entry:45 %vsqrt.i = tail call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)46 ret <4 x half> %vsqrt.i47}48 49define dso_local <8 x half> @t_vsqrtq_f16(<8 x half> %a) {50; CHECK-LABEL: t_vsqrtq_f16:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: fsqrt v0.8h, v0.8h53; CHECK-NEXT: ret54entry:55 %vsqrt.i = tail call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)56 ret <8 x half> %vsqrt.i57}58 59define <4 x i16> @t_fcvtzs_v4i16_v4f16(<4 x half> %a) {60; CHECK-LABEL: t_fcvtzs_v4i16_v4f16:61; CHECK: // %bb.0: // %entry62; CHECK-NEXT: fcvtzs v0.4h, v0.4h63; CHECK-NEXT: ret64entry:65 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtzs.v4i16.v4f16(<4 x half> %a)66 ret <4 x i16> %vcvt67}68 69define <4 x i16> @t_fcvtzu_v4i16_v4f16(<4 x half> %a) {70; CHECK-LABEL: t_fcvtzu_v4i16_v4f16:71; CHECK: // %bb.0: // %entry72; CHECK-NEXT: fcvtzu v0.4h, v0.4h73; CHECK-NEXT: ret74entry:75 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtzu.v4i16.v4f16(<4 x half> %a)76 ret <4 x i16> %vcvt77}78 79define <4 x i16> @t_fcvtas_v4i16_v4f16(<4 x half> %a) {80; CHECK-LABEL: t_fcvtas_v4i16_v4f16:81; CHECK: // %bb.0: // %entry82; CHECK-NEXT: fcvtas v0.4h, v0.4h83; CHECK-NEXT: ret84entry:85 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> %a)86 ret <4 x i16> %vcvt87}88 89define <4 x i16> @t_fcvtau_v4i16_v4f16(<4 x half> %a) {90; CHECK-LABEL: t_fcvtau_v4i16_v4f16:91; CHECK: // %bb.0: // %entry92; CHECK-NEXT: fcvtau v0.4h, v0.4h93; CHECK-NEXT: ret94entry:95 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half> %a)96 ret <4 x i16> %vcvt97}98 99define <4 x i16> @t_fcvtms_v4i16_v4f16(<4 x half> %a) {100; CHECK-LABEL: t_fcvtms_v4i16_v4f16:101; CHECK: // %bb.0: // %entry102; CHECK-NEXT: fcvtms v0.4h, v0.4h103; CHECK-NEXT: ret104entry:105 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half> %a)106 ret <4 x i16> %vcvt107}108 109define <4 x i16> @t_fcvtmu_v4i16_v4f16(<4 x half> %a) {110; CHECK-LABEL: t_fcvtmu_v4i16_v4f16:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: fcvtmu v0.4h, v0.4h113; CHECK-NEXT: ret114entry:115 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half> %a)116 ret <4 x i16> %vcvt117}118 119define <4 x i16> @t_fcvtns_v4i16_v4f16(<4 x half> %a) {120; CHECK-LABEL: t_fcvtns_v4i16_v4f16:121; CHECK: // %bb.0: // %entry122; CHECK-NEXT: fcvtns v0.4h, v0.4h123; CHECK-NEXT: ret124entry:125 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half> %a)126 ret <4 x i16> %vcvt127}128 129define <4 x i16> @t_fcvtnu_v4i16_v4f16(<4 x half> %a) {130; CHECK-LABEL: t_fcvtnu_v4i16_v4f16:131; CHECK: // %bb.0: // %entry132; CHECK-NEXT: fcvtnu v0.4h, v0.4h133; CHECK-NEXT: ret134entry:135 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half> %a)136 ret <4 x i16> %vcvt137}138 139define <4 x i16> @t_fcvtps_v4i16_v4f16(<4 x half> %a) {140; CHECK-LABEL: t_fcvtps_v4i16_v4f16:141; CHECK: // %bb.0: // %entry142; CHECK-NEXT: fcvtps v0.4h, v0.4h143; CHECK-NEXT: ret144entry:145 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half> %a)146 ret <4 x i16> %vcvt147}148 149define <4 x i16> @t_fcvtpu_v4i16_v4f16(<4 x half> %a) {150; CHECK-LABEL: t_fcvtpu_v4i16_v4f16:151; CHECK: // %bb.0: // %entry152; CHECK-NEXT: fcvtpu v0.4h, v0.4h153; CHECK-NEXT: ret154entry:155 %vcvt = tail call <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half> %a)156 ret <4 x i16> %vcvt157}158