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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefixes=GFX7 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s4 5define amdgpu_ps void @store_uniform_P1_addr_i8(i8 %a, ptr addrspace(1) inreg %out) {6; GFX7-LABEL: store_uniform_P1_addr_i8:7; GFX7: ; %bb.0:8; GFX7-NEXT: s_mov_b32 s2, -19; GFX7-NEXT: s_mov_b32 s3, 0xf00010; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 011; GFX7-NEXT: s_endpgm12;13; GFX12-LABEL: store_uniform_P1_addr_i8:14; GFX12: ; %bb.0:15; GFX12-NEXT: v_mov_b32_e32 v1, 016; GFX12-NEXT: global_store_b8 v1, v0, s[0:1]17; GFX12-NEXT: s_endpgm18 store i8 %a, ptr addrspace(1) %out19 ret void20}21 22define amdgpu_ps void @store_uniform_P1_addr_i16(i16 %a, ptr addrspace(1) inreg %out) {23; GFX7-LABEL: store_uniform_P1_addr_i16:24; GFX7: ; %bb.0:25; GFX7-NEXT: s_mov_b32 s2, -126; GFX7-NEXT: s_mov_b32 s3, 0xf00027; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 028; GFX7-NEXT: s_endpgm29;30; GFX12-LABEL: store_uniform_P1_addr_i16:31; GFX12: ; %bb.0:32; GFX12-NEXT: v_mov_b32_e32 v1, 033; GFX12-NEXT: global_store_b16 v1, v0, s[0:1]34; GFX12-NEXT: s_endpgm35 store i16 %a, ptr addrspace(1) %out36 ret void37}38 39define amdgpu_ps void @store_uniform_P1_addr_i32(i32 %a, ptr addrspace(1) inreg %out) {40; GFX7-LABEL: store_uniform_P1_addr_i32:41; GFX7: ; %bb.0:42; GFX7-NEXT: s_mov_b32 s2, -143; GFX7-NEXT: s_mov_b32 s3, 0xf00044; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 045; GFX7-NEXT: s_endpgm46;47; GFX12-LABEL: store_uniform_P1_addr_i32:48; GFX12: ; %bb.0:49; GFX12-NEXT: v_mov_b32_e32 v1, 050; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]51; GFX12-NEXT: s_endpgm52 store i32 %a, ptr addrspace(1) %out53 ret void54}55 56define amdgpu_ps void @store_uniform_P1_addr_v2i32(<2 x i32> %a, ptr addrspace(1) inreg %out) {57; GFX7-LABEL: store_uniform_P1_addr_v2i32:58; GFX7: ; %bb.0:59; GFX7-NEXT: s_mov_b32 s2, -160; GFX7-NEXT: s_mov_b32 s3, 0xf00061; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 062; GFX7-NEXT: s_endpgm63;64; GFX12-LABEL: store_uniform_P1_addr_v2i32:65; GFX12: ; %bb.0:66; GFX12-NEXT: v_mov_b32_e32 v2, 067; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]68; GFX12-NEXT: s_endpgm69 store <2 x i32> %a, ptr addrspace(1) %out70 ret void71}72 73define amdgpu_ps void @store_uniform_P1_addr_v3i32(<3 x i32> %a, ptr addrspace(1) inreg %out) {74; GFX7-LABEL: store_uniform_P1_addr_v3i32:75; GFX7: ; %bb.0:76; GFX7-NEXT: s_mov_b32 s2, -177; GFX7-NEXT: s_mov_b32 s3, 0xf00078; GFX7-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 079; GFX7-NEXT: s_endpgm80;81; GFX12-LABEL: store_uniform_P1_addr_v3i32:82; GFX12: ; %bb.0:83; GFX12-NEXT: v_mov_b32_e32 v3, 084; GFX12-NEXT: global_store_b96 v3, v[0:2], s[0:1]85; GFX12-NEXT: s_endpgm86 store <3 x i32> %a, ptr addrspace(1) %out87 ret void88}89 90define amdgpu_ps void @store_uniform_P1_addr_v4i32(<4 x i32> %a, ptr addrspace(1) inreg %out) {91; GFX7-LABEL: store_uniform_P1_addr_v4i32:92; GFX7: ; %bb.0:93; GFX7-NEXT: s_mov_b32 s2, -194; GFX7-NEXT: s_mov_b32 s3, 0xf00095; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 096; GFX7-NEXT: s_endpgm97;98; GFX12-LABEL: store_uniform_P1_addr_v4i32:99; GFX12: ; %bb.0:100; GFX12-NEXT: v_mov_b32_e32 v4, 0101; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]102; GFX12-NEXT: s_endpgm103 store <4 x i32> %a, ptr addrspace(1) %out104 ret void105}106