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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s3 4; SGPR phi ends up with VGPR inputs. Make sure we do not try to5; process a copy which has already been erased (which was already6; inserted by the pass).7 8define double @issue130646(i64 %arg) {9; CHECK-LABEL: issue130646:10; CHECK: ; %bb.0: ; %entry11; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; CHECK-NEXT: v_mov_b32_e32 v2, 013; CHECK-NEXT: v_mov_b32_e32 v3, 014; CHECK-NEXT: s_mov_b64 s[4:5], 015; CHECK-NEXT: s_branch .LBB0_216; CHECK-NEXT: .LBB0_1: ; %for.body.517; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=118; CHECK-NEXT: s_lshr_b64 s[6:7], s[4:5], 119; CHECK-NEXT: v_or_b32_e32 v3, s7, v320; CHECK-NEXT: v_or_b32_e32 v2, s6, v221; CHECK-NEXT: s_lshr_b64 s[6:7], s[4:5], 522; CHECK-NEXT: s_or_b32 s6, s6, 123; CHECK-NEXT: v_or3_b32 v3, v3, v1, s724; CHECK-NEXT: v_or3_b32 v2, v2, v0, s625; CHECK-NEXT: s_lshr_b64 s[4:5], s[4:5], 826; CHECK-NEXT: s_cbranch_execz .LBB0_427; CHECK-NEXT: .LBB0_2: ; %for.body28; CHECK-NEXT: ; =>This Inner Loop Header: Depth=129; CHECK-NEXT: s_cmp_eq_u64 s[4:5], 030; CHECK-NEXT: v_readfirstlane_b32 s8, v031; CHECK-NEXT: v_readfirstlane_b32 s9, v132; CHECK-NEXT: s_cbranch_scc0 .LBB0_133; CHECK-NEXT: ; %bb.3:34; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr335; CHECK-NEXT: s_mov_b64 s[4:5], s[8:9]36; CHECK-NEXT: .LBB0_4: ; %for.cond.cleanup37; CHECK-NEXT: v_mov_b32_e32 v0, 038; CHECK-NEXT: v_mov_b32_e32 v1, 039; CHECK-NEXT: s_setpc_b64 s[30:31]40entry:41 br label %for.body42 43for.cond.cleanup: ; preds = %for.body44 %cmp3.not.i.i.i = icmp eq i64 %r.0108, 045 br i1 %cmp3.not.i.i.i, label %cleanup, label %if.end26.i.i46 47if.end26.i.i: ; preds = %for.cond.cleanup48 br label %cleanup49 50for.body: ; preds = %for.body.5, %entry51 %current_bit.01093 = phi i64 [ 0, %entry ], [ %shr.3.7, %for.body.5 ]52 %r.0108 = phi i64 [ 0, %entry ], [ %shl28.3.7, %for.body.5 ]53 %shr.3 = lshr i64 %current_bit.01093, 154 %i = or i64 %r.0108, %shr.355 %i3 = or i64 %i, %arg56 %tobool27.not.3.4 = icmp ult i64 %current_bit.01093, 157 br i1 %tobool27.not.3.4, label %for.cond.cleanup, label %for.body.558 59for.body.5: ; preds = %for.body60 %shr.3.4 = lshr i64 %current_bit.01093, 561 %i6 = or i64 %shr.3.4, 162 %shl28.3.7 = or i64 %i6, %i363 %shr.3.7 = lshr i64 %current_bit.01093, 864 br label %for.body65 66cleanup: ; preds = %if.end26.i.i, %for.cond.cleanup67 ret double 0.000000e+0068}69 70define amdgpu_cs void @issue130119(i1 %arg) {71; CHECK-LABEL: issue130119:72; CHECK: ; %bb.0: ; %bb73; CHECK-NEXT: v_and_b32_e32 v0, 1, v074; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v075; CHECK-NEXT: s_mov_b32 s16, 076; CHECK-NEXT: s_mov_b64 s[4:5], 077; CHECK-NEXT: s_branch .LBB1_278; CHECK-NEXT: .LBB1_1: ; %Flow279; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=180; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]81; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]82; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]83; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]84; CHECK-NEXT: s_cbranch_execz .LBB1_1085; CHECK-NEXT: .LBB1_2: ; %bb186; CHECK-NEXT: ; =>This Loop Header: Depth=187; CHECK-NEXT: ; Child Loop BB1_4 Depth 288; CHECK-NEXT: s_and_b32 s2, s16, 189; CHECK-NEXT: s_cmp_eq_u32 s2, 090; CHECK-NEXT: s_cselect_b64 s[6:7], -1, 091; CHECK-NEXT: s_cmp_eq_u32 s2, 192; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 093; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]94; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, v095; CHECK-NEXT: s_mov_b64 s[10:11], 096; CHECK-NEXT: ; implicit-def: $sgpr8_sgpr997; CHECK-NEXT: s_branch .LBB1_498; CHECK-NEXT: .LBB1_3: ; %Flow199; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2100; CHECK-NEXT: s_xor_b64 s[14:15], s[14:15], -1101; CHECK-NEXT: s_and_b64 s[12:13], exec, s[12:13]102; CHECK-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]103; CHECK-NEXT: s_andn2_b64 s[8:9], s[8:9], exec104; CHECK-NEXT: s_and_b64 s[12:13], s[14:15], exec105; CHECK-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]106; CHECK-NEXT: s_andn2_b64 exec, exec, s[10:11]107; CHECK-NEXT: s_cbranch_execz .LBB1_8108; CHECK-NEXT: .LBB1_4: ; %bb3109; CHECK-NEXT: ; Parent Loop BB1_2 Depth=1110; CHECK-NEXT: ; => This Inner Loop Header: Depth=2111; CHECK-NEXT: s_and_b64 vcc, exec, s[2:3]112; CHECK-NEXT: s_mov_b64 s[14:15], s[6:7]113; CHECK-NEXT: s_cbranch_vccnz .LBB1_6114; CHECK-NEXT: ; %bb.5: ; %bb7115; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2116; CHECK-NEXT: s_mov_b64 s[14:15], -1117; CHECK-NEXT: .LBB1_6: ; %Flow118; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2119; CHECK-NEXT: s_mov_b64 s[12:13], -1120; CHECK-NEXT: s_andn2_b64 vcc, exec, s[14:15]121; CHECK-NEXT: s_mov_b64 s[14:15], -1122; CHECK-NEXT: s_cbranch_vccnz .LBB1_3123; CHECK-NEXT: ; %bb.7: ; %bb8124; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2125; CHECK-NEXT: s_mov_b64 s[14:15], 0126; CHECK-NEXT: s_orn2_b64 s[12:13], s[0:1], exec127; CHECK-NEXT: s_branch .LBB1_3128; CHECK-NEXT: .LBB1_8: ; %loop.exit.guard129; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1130; CHECK-NEXT: s_or_b64 exec, exec, s[10:11]131; CHECK-NEXT: s_mov_b64 s[2:3], -1132; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]133; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]134; CHECK-NEXT: s_cbranch_execz .LBB1_1135; CHECK-NEXT: ; %bb.9: ; %bb10136; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1137; CHECK-NEXT: s_or_b32 s16, s16, 1138; CHECK-NEXT: s_xor_b64 s[2:3], exec, -1139; CHECK-NEXT: s_branch .LBB1_1140; CHECK-NEXT: .LBB1_10: ; %DummyReturnBlock141; CHECK-NEXT: s_endpgm142bb:143 br label %bb1144 145bb1: ; preds = %bb10, %bb146 %i = phi i32 [ 0, %bb ], [ %i11, %bb10 ]147 %i2 = phi i32 [ 0, %bb ], [ %i4, %bb10 ]148 br label %bb3149 150bb3: ; preds = %bb8, %bb1151 %i4 = phi i32 [ %i2, %bb1 ], [ %i9, %bb8 ]152 %i5 = and i32 %i, 1153 %i6 = icmp eq i32 %i5, 0154 br i1 %i6, label %bb8, label %bb7155 156bb7: ; preds = %bb3157 br label %bb8158 159bb8: ; preds = %bb7, %bb3160 %i9 = phi i32 [ %i2, %bb3 ], [ 0, %bb7 ]161 br i1 %arg, label %bb10, label %bb3162 163bb10: ; preds = %bb8164 %i11 = or i32 %i, 1165 br label %bb1166}167