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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx %s -o - | FileCheck %s --check-prefix=LA323; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s --check-prefix=LA644 5define void @vec_reduce_add_v32i8(ptr %src, ptr %dst) nounwind {6; LA32-LABEL: vec_reduce_add_v32i8:7; LA32: # %bb.0:8; LA32-NEXT: xvld $xr0, $a0, 09; LA32-NEXT: xvhaddw.h.b $xr0, $xr0, $xr010; LA32-NEXT: xvhaddw.w.h $xr0, $xr0, $xr011; LA32-NEXT: xvhaddw.d.w $xr0, $xr0, $xr012; LA32-NEXT: xvhaddw.q.d $xr0, $xr0, $xr013; LA32-NEXT: xvpermi.d $xr1, $xr0, 214; LA32-NEXT: xvadd.d $xr0, $xr1, $xr015; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 016; LA32-NEXT: st.b $a0, $a1, 017; LA32-NEXT: ret18;19; LA64-LABEL: vec_reduce_add_v32i8:20; LA64: # %bb.0:21; LA64-NEXT: xvld $xr0, $a0, 022; LA64-NEXT: xvhaddw.h.b $xr0, $xr0, $xr023; LA64-NEXT: xvhaddw.w.h $xr0, $xr0, $xr024; LA64-NEXT: xvhaddw.d.w $xr0, $xr0, $xr025; LA64-NEXT: xvhaddw.q.d $xr0, $xr0, $xr026; LA64-NEXT: xvpermi.d $xr1, $xr0, 227; LA64-NEXT: xvadd.d $xr0, $xr1, $xr028; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 029; LA64-NEXT: st.b $a0, $a1, 030; LA64-NEXT: ret31 %v = load <32 x i8>, ptr %src32 %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v)33 store i8 %res, ptr %dst34 ret void35}36 37define void @vec_reduce_add_v16i16(ptr %src, ptr %dst) nounwind {38; LA32-LABEL: vec_reduce_add_v16i16:39; LA32: # %bb.0:40; LA32-NEXT: xvld $xr0, $a0, 041; LA32-NEXT: xvhaddw.w.h $xr0, $xr0, $xr042; LA32-NEXT: xvhaddw.d.w $xr0, $xr0, $xr043; LA32-NEXT: xvhaddw.q.d $xr0, $xr0, $xr044; LA32-NEXT: xvpermi.d $xr1, $xr0, 245; LA32-NEXT: xvadd.d $xr0, $xr1, $xr046; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 047; LA32-NEXT: st.h $a0, $a1, 048; LA32-NEXT: ret49;50; LA64-LABEL: vec_reduce_add_v16i16:51; LA64: # %bb.0:52; LA64-NEXT: xvld $xr0, $a0, 053; LA64-NEXT: xvhaddw.w.h $xr0, $xr0, $xr054; LA64-NEXT: xvhaddw.d.w $xr0, $xr0, $xr055; LA64-NEXT: xvhaddw.q.d $xr0, $xr0, $xr056; LA64-NEXT: xvpermi.d $xr1, $xr0, 257; LA64-NEXT: xvadd.d $xr0, $xr1, $xr058; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 059; LA64-NEXT: st.h $a0, $a1, 060; LA64-NEXT: ret61 %v = load <16 x i16>, ptr %src62 %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v)63 store i16 %res, ptr %dst64 ret void65}66 67define void @vec_reduce_add_v8i32(ptr %src, ptr %dst) nounwind {68; LA32-LABEL: vec_reduce_add_v8i32:69; LA32: # %bb.0:70; LA32-NEXT: xvld $xr0, $a0, 071; LA32-NEXT: xvhaddw.d.w $xr0, $xr0, $xr072; LA32-NEXT: xvhaddw.q.d $xr0, $xr0, $xr073; LA32-NEXT: xvpermi.d $xr1, $xr0, 274; LA32-NEXT: xvadd.d $xr0, $xr1, $xr075; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 076; LA32-NEXT: st.w $a0, $a1, 077; LA32-NEXT: ret78;79; LA64-LABEL: vec_reduce_add_v8i32:80; LA64: # %bb.0:81; LA64-NEXT: xvld $xr0, $a0, 082; LA64-NEXT: xvhaddw.d.w $xr0, $xr0, $xr083; LA64-NEXT: xvhaddw.q.d $xr0, $xr0, $xr084; LA64-NEXT: xvpermi.d $xr1, $xr0, 285; LA64-NEXT: xvadd.d $xr0, $xr1, $xr086; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 087; LA64-NEXT: st.w $a0, $a1, 088; LA64-NEXT: ret89 %v = load <8 x i32>, ptr %src90 %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v)91 store i32 %res, ptr %dst92 ret void93}94 95define void @vec_reduce_add_v4i64(ptr %src, ptr %dst) nounwind {96; LA32-LABEL: vec_reduce_add_v4i64:97; LA32: # %bb.0:98; LA32-NEXT: xvld $xr0, $a0, 099; LA32-NEXT: xvpermi.q $xr1, $xr0, 1100; LA32-NEXT: vadd.d $vr0, $vr0, $vr1101; LA32-NEXT: vpickve2gr.w $a0, $vr0, 3102; LA32-NEXT: vpickve2gr.w $a2, $vr0, 1103; LA32-NEXT: add.w $a0, $a2, $a0104; LA32-NEXT: vpickve2gr.w $a2, $vr0, 2105; LA32-NEXT: vpickve2gr.w $a3, $vr0, 0106; LA32-NEXT: add.w $a2, $a3, $a2107; LA32-NEXT: sltu $a3, $a2, $a3108; LA32-NEXT: add.w $a0, $a0, $a3109; LA32-NEXT: st.w $a2, $a1, 0110; LA32-NEXT: st.w $a0, $a1, 4111; LA32-NEXT: ret112;113; LA64-LABEL: vec_reduce_add_v4i64:114; LA64: # %bb.0:115; LA64-NEXT: xvld $xr0, $a0, 0116; LA64-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0117; LA64-NEXT: xvpermi.d $xr1, $xr0, 2118; LA64-NEXT: xvadd.d $xr0, $xr1, $xr0119; LA64-NEXT: xvstelm.d $xr0, $a1, 0, 0120; LA64-NEXT: ret121 %v = load <4 x i64>, ptr %src122 %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)123 store i64 %res, ptr %dst124 ret void125}126