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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define <16 x i8> @vrepl_ins_b(i32 %a, i32 %b) {6; CHECK-LABEL: vrepl_ins_b:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vreplgr2vr.b $vr0, $a09; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 110; CHECK-NEXT: ret11entry:12 %0 = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a)13 %1 = call <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8> %0, i32 %b, i32 1)14 ret <16 x i8> %115}16 17define <8 x i16> @vrepl_ins_h(i32 %a, i32 %b) {18; CHECK-LABEL: vrepl_ins_h:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: vreplgr2vr.h $vr0, $a021; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 122; CHECK-NEXT: ret23entry:24 %0 = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a)25 %1 = call <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16> %0, i32 %b, i32 1)26 ret <8 x i16> %127}28 29define <4 x i32> @vrepl_ins_w(i32 %a, i32 %b) {30; CHECK-LABEL: vrepl_ins_w:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vreplgr2vr.w $vr0, $a033; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 134; CHECK-NEXT: ret35entry:36 %0 = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a)37 %1 = call <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32> %0, i32 %b, i32 1)38 ret <4 x i32> %139}40 41declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32 immarg)42declare <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32)43declare <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16>, i32, i32 immarg)44declare <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32)45declare <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32>, i32, i32 immarg)46declare <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32)47