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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind {6; CHECK-LABEL: insert_extract_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vextrins.b $vr0, $vr0, 319; CHECK-NEXT: ret10entry:11 %b = extractelement <16 x i8> %a, i32 1512 %c = insertelement <16 x i8> %a, i8 %b, i32 113 ret <16 x i8> %c14}15 16define <8 x i16> @insert_extract_v8i16(<8 x i16> %a) nounwind {17; CHECK-LABEL: insert_extract_v8i16:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vextrins.h $vr0, $vr0, 2320; CHECK-NEXT: ret21entry:22 %b = extractelement <8 x i16> %a, i32 723 %c = insertelement <8 x i16> %a, i16 %b, i32 124 ret <8 x i16> %c25}26 27define <4 x i32> @insert_extract_v4i32(<4 x i32> %a) nounwind {28; CHECK-LABEL: insert_extract_v4i32:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vextrins.w $vr0, $vr0, 1931; CHECK-NEXT: ret32entry:33 %b = extractelement <4 x i32> %a, i32 334 %c = insertelement <4 x i32> %a, i32 %b, i32 135 ret <4 x i32> %c36}37 38define <4 x float> @insert_extract_v4f32(<4 x float> %a) nounwind {39; CHECK-LABEL: insert_extract_v4f32:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vextrins.w $vr0, $vr0, 342; CHECK-NEXT: ret43entry:44 %b = extractelement <4 x float> %a, i32 345 %c = insertelement <4 x float> %a, float %b, i32 046 ret <4 x float> %c47}48 49define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind {50; LA32-LABEL: insert_extract_v2i64:51; LA32: # %bb.0: # %entry52; LA32-NEXT: vori.b $vr1, $vr0, 053; LA32-NEXT: vextrins.w $vr1, $vr0, 254; LA32-NEXT: vextrins.w $vr1, $vr0, 1955; LA32-NEXT: vori.b $vr0, $vr1, 056; LA32-NEXT: ret57;58; LA64-LABEL: insert_extract_v2i64:59; LA64: # %bb.0: # %entry60; LA64-NEXT: vextrins.d $vr0, $vr0, 161; LA64-NEXT: ret62entry:63 %b = extractelement <2 x i64> %a, i32 164 %c = insertelement <2 x i64> %a, i64 %b, i32 065 ret <2 x i64> %c66}67 68define <2 x double> @insert_extract_v2f64(<2 x double> %a) nounwind {69; CHECK-LABEL: insert_extract_v2f64:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: vextrins.d $vr0, $vr0, 172; CHECK-NEXT: ret73entry:74 %b = extractelement <2 x double> %a, i32 175 %c = insertelement <2 x double> %a, double %b, i32 076 ret <2 x double> %c77}78