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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @test_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {8; CHECK-LABEL: test_half_bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a2, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfadd.vv v10, v10, v1113; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma14; CHECK-NEXT: vfadd.vv v8, v8, v915; CHECK-NEXT: fsrm a216; CHECK-NEXT: vse16.v v10, (a1)17; CHECK-NEXT: ret18entry:19 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(20 <vscale x 1 x half> poison,21 <vscale x 1 x half> %3,22 <vscale x 1 x half> %4,23 iXLen 0, iXLen %2)24 25 %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(26 <vscale x 1 x bfloat> poison,27 <vscale x 1 x bfloat> %0,28 <vscale x 1 x bfloat> %1,29 iXLen 0, iXLen %2)30 31 call void @llvm.riscv.vse(<vscale x 1 x half> %a, ptr %ptr, iXLen %2)32 33 ret <vscale x 1 x bfloat> %b34}35 36define <vscale x 1 x bfloat> @test_i32_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i32> %3, <vscale x 1 x i32> %4, ptr %ptr) nounwind {37; CHECK-LABEL: test_i32_bf16:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma40; CHECK-NEXT: vadd.vv v10, v10, v1141; CHECK-NEXT: fsrmi a0, 042; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma43; CHECK-NEXT: vfadd.vv v8, v8, v944; CHECK-NEXT: fsrm a045; CHECK-NEXT: vse32.v v10, (a1)46; CHECK-NEXT: ret47entry:48 %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(49 <vscale x 1 x i32> poison,50 <vscale x 1 x i32> %3,51 <vscale x 1 x i32> %4,52 iXLen %2)53 54 %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(55 <vscale x 1 x bfloat> poison,56 <vscale x 1 x bfloat> %0,57 <vscale x 1 x bfloat> %1,58 iXLen 0, iXLen %2)59 60 call void @llvm.riscv.vse(<vscale x 1 x i32> %a, ptr %ptr, iXLen %2)61 62 ret <vscale x 1 x bfloat> %b63}64 65define <vscale x 1 x bfloat> @test_half_bf16_half(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {66; CHECK-LABEL: test_half_bf16_half:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: fsrmi a2, 069; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma70; CHECK-NEXT: vfadd.vv v10, v10, v1171; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma72; CHECK-NEXT: vfadd.vv v8, v8, v973; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma74; CHECK-NEXT: vfadd.vv v9, v10, v1175; CHECK-NEXT: fsrm a276; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma77; CHECK-NEXT: vse16.v v9, (a1)78; CHECK-NEXT: ret79entry:80 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(81 <vscale x 1 x half> poison,82 <vscale x 1 x half> %3,83 <vscale x 1 x half> %4,84 iXLen 0, iXLen %2)85 86 %b = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(87 <vscale x 1 x bfloat> poison,88 <vscale x 1 x bfloat> %0,89 <vscale x 1 x bfloat> %1,90 iXLen 0, iXLen %2)91 92 %c = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(93 <vscale x 1 x half> poison,94 <vscale x 1 x half> %a,95 <vscale x 1 x half> %4,96 iXLen 0, iXLen %2)97 98 store <vscale x 1 x half> %c, ptr %ptr99 100 ret <vscale x 1 x bfloat> %b101}102 103define <vscale x 1 x bfloat> @test_bf16_half_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x half> %3, <vscale x 1 x half> %4, ptr %ptr) nounwind {104; CHECK-LABEL: test_bf16_half_bf16:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: fsrmi a2, 0107; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma108; CHECK-NEXT: vfadd.vv v8, v8, v9109; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma110; CHECK-NEXT: vfadd.vv v10, v10, v11111; CHECK-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma112; CHECK-NEXT: vfadd.vv v8, v8, v9113; CHECK-NEXT: fsrm a2114; CHECK-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma115; CHECK-NEXT: vse16.v v10, (a1)116; CHECK-NEXT: ret117entry:118 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(119 <vscale x 1 x bfloat> poison,120 <vscale x 1 x bfloat> %0,121 <vscale x 1 x bfloat> %1,122 iXLen 0, iXLen %2)123 124 %b = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(125 <vscale x 1 x half> poison,126 <vscale x 1 x half> %3,127 <vscale x 1 x half> %4,128 iXLen 0, iXLen %2)129 130 %c = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(131 <vscale x 1 x bfloat> poison,132 <vscale x 1 x bfloat> %a,133 <vscale x 1 x bfloat> %1,134 iXLen 0, iXLen %2)135 136 store <vscale x 1 x half> %b, ptr %ptr137 138 ret <vscale x 1 x bfloat> %c139}140 141define <vscale x 1 x bfloat> @test_bf16_i16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i16> %3, <vscale x 1 x i16> %4, ptr %ptr) nounwind {142; CHECK-LABEL: test_bf16_i16:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: fsrmi a2, 0145; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma146; CHECK-NEXT: vfadd.vv v8, v8, v9147; CHECK-NEXT: vadd.vv v9, v10, v11148; CHECK-NEXT: fsrm a2149; CHECK-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma150; CHECK-NEXT: vse16.v v9, (a1)151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16(154 <vscale x 1 x bfloat> poison,155 <vscale x 1 x bfloat> %0,156 <vscale x 1 x bfloat> %1,157 iXLen 0, iXLen %2)158 159 %b = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(160 <vscale x 1 x i16> poison,161 <vscale x 1 x i16> %3,162 <vscale x 1 x i16> %4,163 iXLen %2)164 165 store <vscale x 1 x i16> %b, ptr %ptr166 167 ret <vscale x 1 x bfloat> %a168}169