217 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfmerge_vfm_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1bf16_nxv1bf16_bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16(15 <vscale x 1 x bfloat> poison,16 <vscale x 1 x bfloat> %0,17 bfloat %1,18 <vscale x 1 x i1> %2,19 iXLen %3)20 21 ret <vscale x 1 x bfloat> %a22}23 24define <vscale x 2 x bfloat> @intrinsic_vfmerge_vfm_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2bf16_nxv2bf16_bf16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma28; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v029; CHECK-NEXT: ret30entry:31 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16(32 <vscale x 2 x bfloat> poison,33 <vscale x 2 x bfloat> %0,34 bfloat %1,35 <vscale x 2 x i1> %2,36 iXLen %3)37 38 ret <vscale x 2 x bfloat> %a39}40 41define <vscale x 4 x bfloat> @intrinsic_vfmerge_vfm_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {42; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4bf16_nxv4bf16_bf16:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma45; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v046; CHECK-NEXT: ret47entry:48 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16(49 <vscale x 4 x bfloat> poison,50 <vscale x 4 x bfloat> %0,51 bfloat %1,52 <vscale x 4 x i1> %2,53 iXLen %3)54 55 ret <vscale x 4 x bfloat> %a56}57 58define <vscale x 8 x bfloat> @intrinsic_vfmerge_vfm_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {59; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8bf16_nxv8bf16_bf16:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma62; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v063; CHECK-NEXT: ret64entry:65 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16(66 <vscale x 8 x bfloat> poison,67 <vscale x 8 x bfloat> %0,68 bfloat %1,69 <vscale x 8 x i1> %2,70 iXLen %3)71 72 ret <vscale x 8 x bfloat> %a73}74 75define <vscale x 16 x bfloat> @intrinsic_vfmerge_vfm_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {76; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16bf16_nxv16bf16_bf16:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma79; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v080; CHECK-NEXT: ret81entry:82 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16(83 <vscale x 16 x bfloat> poison,84 <vscale x 16 x bfloat> %0,85 bfloat %1,86 <vscale x 16 x i1> %2,87 iXLen %3)88 89 ret <vscale x 16 x bfloat> %a90}91 92define <vscale x 32 x bfloat> @intrinsic_vfmerge_vfm_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {93; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32bf16_nxv32bf16_bf16:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma96; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v097; CHECK-NEXT: ret98entry:99 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16(100 <vscale x 32 x bfloat> poison,101 <vscale x 32 x bfloat> %0,102 bfloat %1,103 <vscale x 32 x i1> %2,104 iXLen %3)105 106 ret <vscale x 32 x bfloat> %a107}108 109define <vscale x 1 x bfloat> @intrinsic_vfmerge_vzm_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1bf16_nxv1bf16_bf16:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: fmv.h.x fa5, zero113; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma114; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16(118 <vscale x 1 x bfloat> poison,119 <vscale x 1 x bfloat> %0,120 bfloat zeroinitializer,121 <vscale x 1 x i1> %1,122 iXLen %2)123 124 ret <vscale x 1 x bfloat> %a125}126 127define <vscale x 2 x bfloat> @intrinsic_vfmerge_vzm_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {128; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2bf16_nxv2bf16_bf16:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: fmv.h.x fa5, zero131; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma132; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0133; CHECK-NEXT: ret134entry:135 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16(136 <vscale x 2 x bfloat> poison,137 <vscale x 2 x bfloat> %0,138 bfloat zeroinitializer,139 <vscale x 2 x i1> %1,140 iXLen %2)141 142 ret <vscale x 2 x bfloat> %a143}144 145define <vscale x 4 x bfloat> @intrinsic_vfmerge_vzm_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {146; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4bf16_nxv4bf16_bf16:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: fmv.h.x fa5, zero149; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma150; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16(154 <vscale x 4 x bfloat> poison,155 <vscale x 4 x bfloat> %0,156 bfloat zeroinitializer,157 <vscale x 4 x i1> %1,158 iXLen %2)159 160 ret <vscale x 4 x bfloat> %a161}162 163define <vscale x 8 x bfloat> @intrinsic_vfmerge_vzm_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8bf16_nxv8bf16_bf16:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: fmv.h.x fa5, zero167; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma168; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0169; CHECK-NEXT: ret170entry:171 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16(172 <vscale x 8 x bfloat> poison,173 <vscale x 8 x bfloat> %0,174 bfloat zeroinitializer,175 <vscale x 8 x i1> %1,176 iXLen %2)177 178 ret <vscale x 8 x bfloat> %a179}180 181define <vscale x 16 x bfloat> @intrinsic_vfmerge_vzm_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {182; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16bf16_nxv16bf16_bf16:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: fmv.h.x fa5, zero185; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma186; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0187; CHECK-NEXT: ret188entry:189 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16(190 <vscale x 16 x bfloat> poison,191 <vscale x 16 x bfloat> %0,192 bfloat zeroinitializer,193 <vscale x 16 x i1> %1,194 iXLen %2)195 196 ret <vscale x 16 x bfloat> %a197}198 199define <vscale x 32 x bfloat> @intrinsic_vfmerge_vzm_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {200; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32bf16_nxv32bf16_bf16:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: fmv.h.x fa5, zero203; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma204; CHECK-NEXT: vfmerge.vfm v8, v8, fa5, v0205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16(208 <vscale x 32 x bfloat> poison,209 <vscale x 32 x bfloat> %0,210 bfloat zeroinitializer,211 <vscale x 32 x i1> %1,212 iXLen %2)213 214 ret <vscale x 32 x bfloat> %a215}216 217