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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) #0 {5; CHECK-LABEL: test_vaddq_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vadd.f16 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x half> @llvm.arm.mve.vadd.v8f16(<8 x half> %a, <8 x half> %b)11 ret <8 x half> %012}13 14define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32(<4 x float> %a, <4 x float> %b) #0 {15; CHECK-LABEL: test_vaddq_f32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vadd.f32 q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = tail call <4 x float> @llvm.arm.mve.vadd.v4f32(<4 x float> %a, <4 x float> %b)21 ret <4 x float> %022}23 24define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) #0 {25; CHECK-LABEL: test_vsubq_f16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vsub.f16 q0, q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = tail call <8 x half> @llvm.arm.mve.vsub.v8f16(<8 x half> %a, <8 x half> %b)31 ret <8 x half> %032}33 34define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32(<4 x float> %a, <4 x float> %b) #0 {35; CHECK-LABEL: test_vsubq_f32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vsub.f32 q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = tail call <4 x float> @llvm.arm.mve.vsub.v4f32(<4 x float> %a, <4 x float> %b)41 ret <4 x float> %042}43 44define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) #0 {45; CHECK-LABEL: test_vmulq_f16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vmul.f16 q0, q0, q148; CHECK-NEXT: bx lr49entry:50 %0 = tail call <8 x half> @llvm.arm.mve.vmul.v8f16(<8 x half> %a, <8 x half> %b)51 ret <8 x half> %052}53 54define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) #0 {55; CHECK-LABEL: test_vmulq_f32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vmul.f32 q0, q0, q158; CHECK-NEXT: bx lr59entry:60 %0 = tail call <4 x float> @llvm.arm.mve.vmul.v4f32(<4 x float> %a, <4 x float> %b)61 ret <4 x float> %062}63 64 65 66 67define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16_splat(<8 x half> %a, half %b) #0 {68; CHECK-LABEL: test_vaddq_f16_splat:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: vmov.f16 r0, s471; CHECK-NEXT: vadd.f16 q0, q0, r072; CHECK-NEXT: bx lr73entry:74 %i = insertelement <8 x half> poison, half %b, i32 075 %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer76 %0 = tail call <8 x half> @llvm.arm.mve.vadd.v8f16(<8 x half> %a, <8 x half> %s)77 ret <8 x half> %078}79 80define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32_splat(<4 x float> %a, float %b) #0 {81; CHECK-LABEL: test_vaddq_f32_splat:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vmov r0, s484; CHECK-NEXT: vadd.f32 q0, q0, r085; CHECK-NEXT: bx lr86entry:87 %i = insertelement <4 x float> poison, float %b, i32 088 %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer89 %0 = tail call <4 x float> @llvm.arm.mve.vadd.v4f32(<4 x float> %a, <4 x float> %s)90 ret <4 x float> %091}92 93define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16_splat(<8 x half> %a, half %b) #0 {94; CHECK-LABEL: test_vsubq_f16_splat:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: vmov.f16 r0, s497; CHECK-NEXT: vsub.f16 q0, q0, r098; CHECK-NEXT: bx lr99entry:100 %i = insertelement <8 x half> poison, half %b, i32 0101 %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer102 %0 = tail call <8 x half> @llvm.arm.mve.vsub.v8f16(<8 x half> %a, <8 x half> %s)103 ret <8 x half> %0104}105 106define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32_splat(<4 x float> %a, float %b) #0 {107; CHECK-LABEL: test_vsubq_f32_splat:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmov r0, s4110; CHECK-NEXT: vsub.f32 q0, q0, r0111; CHECK-NEXT: bx lr112entry:113 %i = insertelement <4 x float> poison, float %b, i32 0114 %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer115 %0 = tail call <4 x float> @llvm.arm.mve.vsub.v4f32(<4 x float> %a, <4 x float> %s)116 ret <4 x float> %0117}118 119define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16_splat(<8 x half> %a, half %b) #0 {120; CHECK-LABEL: test_vmulq_f16_splat:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmov.f16 r0, s4123; CHECK-NEXT: vmul.f16 q0, q0, r0124; CHECK-NEXT: bx lr125entry:126 %i = insertelement <8 x half> poison, half %b, i32 0127 %s = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer128 %0 = tail call <8 x half> @llvm.arm.mve.vmul.v8f16(<8 x half> %a, <8 x half> %s)129 ret <8 x half> %0130}131 132define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32_splat(<4 x float> %a, float %b) #0 {133; CHECK-LABEL: test_vmulq_f32_splat:134; CHECK: @ %bb.0: @ %entry135; CHECK-NEXT: vmov r0, s4136; CHECK-NEXT: vmul.f32 q0, q0, r0137; CHECK-NEXT: bx lr138entry:139 %i = insertelement <4 x float> poison, float %b, i32 0140 %s = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer141 %0 = tail call <4 x float> @llvm.arm.mve.vmul.v4f32(<4 x float> %a, <4 x float> %s)142 ret <4 x float> %0143}144 145define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {146; CHECK-LABEL: fma_v4f32:147; CHECK: @ %bb.0: @ %entry148; CHECK-NEXT: vfma.f32 q0, q1, q2149; CHECK-NEXT: bx lr150entry:151 %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %s1, <4 x float> %s2, <4 x float> %dst)152 ret <4 x float> %0153}154 155define arm_aapcs_vfpcc <8 x half> @fma_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {156; CHECK-LABEL: fma_v8f16:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: vfma.f16 q0, q1, q2159; CHECK-NEXT: bx lr160entry:161 %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %s1, <8 x half> %s2, <8 x half> %dst)162 ret <8 x half> %0163}164 165define arm_aapcs_vfpcc <4 x float> @fma_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {166; CHECK-LABEL: fma_n_v8f16:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmov r0, s8169; CHECK-NEXT: vfma.f32 q0, q1, r0170; CHECK-NEXT: bx lr171entry:172 %i = insertelement <4 x float> poison, float %s3, i32 0173 %sp = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer174 %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %s2, <4 x float> %sp, <4 x float> %s1)175 ret <4 x float> %0176}177 178define arm_aapcs_vfpcc <8 x half> @fma_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {179; CHECK-LABEL: fma_n_v4f32:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: vmov.f16 r0, s8182; CHECK-NEXT: vfma.f16 q0, q1, r0183; CHECK-NEXT: bx lr184entry:185 %i = insertelement <8 x half> poison, half %s3, i32 0186 %sp = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer187 %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %s2, <8 x half> %sp, <8 x half> %s1)188 ret <8 x half> %0189}190 191define arm_aapcs_vfpcc <4 x float> @fms_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {192; CHECK-LABEL: fms_v4f32:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vfms.f32 q0, q1, q2195; CHECK-NEXT: bx lr196entry:197 %c = fneg <4 x float> %s1198 %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %c, <4 x float> %s2, <4 x float> %dst)199 ret <4 x float> %0200}201 202define arm_aapcs_vfpcc <8 x half> @fms_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {203; CHECK-LABEL: fms_v8f16:204; CHECK: @ %bb.0: @ %entry205; CHECK-NEXT: vfms.f16 q0, q1, q2206; CHECK-NEXT: bx lr207entry:208 %c = fneg <8 x half> %s1209 %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %c, <8 x half> %s2, <8 x half> %dst)210 ret <8 x half> %0211}212 213define arm_aapcs_vfpcc <4 x float> @fms_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {214; CHECK-LABEL: fms_n_v8f16:215; CHECK: @ %bb.0: @ %entry216; CHECK-NEXT: vmov r0, s8217; CHECK-NEXT: vdup.32 q2, r0218; CHECK-NEXT: vfms.f32 q0, q1, q2219; CHECK-NEXT: bx lr220entry:221 %c = fneg <4 x float> %s2222 %i = insertelement <4 x float> poison, float %s3, i32 0223 %sp = shufflevector <4 x float> %i, <4 x float> poison, <4 x i32> zeroinitializer224 %0 = tail call <4 x float> @llvm.arm.mve.fma.v4f32(<4 x float> %c, <4 x float> %sp, <4 x float> %s1)225 ret <4 x float> %0226}227 228define arm_aapcs_vfpcc <8 x half> @fms_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {229; CHECK-LABEL: fms_n_v4f32:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vmov.f16 r0, s8232; CHECK-NEXT: vdup.16 q2, r0233; CHECK-NEXT: vfms.f16 q0, q1, q2234; CHECK-NEXT: bx lr235entry:236 %c = fneg <8 x half> %s2237 %i = insertelement <8 x half> poison, half %s3, i32 0238 %sp = shufflevector <8 x half> %i, <8 x half> poison, <8 x i32> zeroinitializer239 %0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %c, <8 x half> %sp, <8 x half> %s1)240 ret <8 x half> %0241}242 243attributes #0 = { strictfp }