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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes="gvn-sink" -S %s | FileCheck %s3 4;; See https://github.com/llvm/llvm-project/issues/138345 for details.5;; The program below used to crash due to taking the address of the inline asm.6;; gvn-sink shouldn't do anything in this case, so test that the pass no longer7;; generates invalid IR and no longer crashes.8 9define void @c(i64 %num, ptr %ptr) {10; CHECK-LABEL: define void @c(11; CHECK-SAME: i64 [[NUM:%.*]], ptr [[PTR:%.*]]) {12; CHECK-NEXT: [[ENTRY:.*:]]13; CHECK-NEXT: switch i64 [[NUM]], label %[[SW_EPILOG:.*]] [14; CHECK-NEXT: i64 1, label %[[SW_BB:.*]]15; CHECK-NEXT: i64 0, label %[[SW_BB1:.*]]16; CHECK-NEXT: ]17; CHECK: [[SW_BB]]:18; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[PTR]], align 119; CHECK-NEXT: call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP1]], ptr @c)20; CHECK-NEXT: br label %[[SW_EPILOG]]21; CHECK: [[SW_BB1]]:22; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[PTR]], align 123; CHECK-NEXT: call void asm sideeffect "movdqu 0 [[XMM0:%.*]] \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP2]], ptr @c)24; CHECK-NEXT: br label %[[SW_EPILOG]]25; CHECK: [[SW_EPILOG]]:26; CHECK-NEXT: ret void27;28entry:29 switch i64 %num, label %sw.epilog [30 i64 1, label %sw.bb31 i64 0, label %sw.bb132 ]33 34sw.bb: ; preds = %entry35 %1 = load i8, ptr %ptr, align 136 call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %1, ptr @c)37 br label %sw.epilog38 39sw.bb1: ; preds = %entry40 %2 = load i8, ptr %ptr, align 141 call void asm sideeffect "movdqu 0 %xmm0 \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %2, ptr @c)42 br label %sw.epilog43 44sw.epilog: ; preds = %sw.bb1, %sw.bb, %entry45 ret void46}47