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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 62; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i32 @LHSBin(i1 %C) !prof !0 {5; CHECK-LABEL: define i32 @LHSBin(6; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0:![0-9]+]] {7; CHECK-NEXT: [[V:%.*]] = select i1 [[C]], i32 1010, i32 20, !prof [[PROF1:![0-9]+]]8; CHECK-NEXT: ret i32 [[V]]9;10 %A = select i1 %C, i32 1000, i32 10, !prof !111 %V = add i32 %A, 1012 ret i32 %V13}14 15define i32 @RHSBin(i1 %C) !prof !0 {16; CHECK-LABEL: define i32 @RHSBin(17; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {18; CHECK-NEXT: [[V:%.*]] = select i1 [[C]], i32 1010, i32 20, !prof [[PROF1]]19; CHECK-NEXT: ret i32 [[V]]20;21 %A = select i1 %C, i32 1000, i32 10, !prof !122 %V = add i32 10, %A23 ret i32 %V;24}25 26define i32 @BothBin(i1 %C) !prof !0 {27; CHECK-LABEL: define i32 @BothBin(28; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {29; CHECK-NEXT: [[V:%.*]] = select i1 [[C]], i32 2000, i32 20, !prof [[PROF1]]30; CHECK-NEXT: ret i32 [[V]]31;32 %A = select i1 %C, i32 1000, i32 10, !prof !133 %B = select i1 %C, i32 1000, i32 10, !prof !134 %V = add i32 %A, %B35 ret i32 %V;36}37 38define i32 @NegBin(i1 %C) !prof !0 {39; CHECK-LABEL: define i32 @NegBin(40; CHECK-SAME: i1 [[C:%.*]]) !prof [[PROF0]] {41; CHECK-NEXT: [[V:%.*]] = select i1 [[C]], i32 1010, i32 0, !prof [[PROF1]]42; CHECK-NEXT: ret i32 [[V]]43;44 %A = select i1 %C, i32 1000, i32 -10, !prof !145 %V = add i32 %A, 1046 ret i32 %V47}48 49define i32 @select_C_minus_1_or_C_from_bool(i1 %x) !prof !0 {50; CHECK-LABEL: define i32 @select_C_minus_1_or_C_from_bool(51; CHECK-SAME: i1 [[X:%.*]]) !prof [[PROF0]] {52; CHECK-NEXT: [[ADD:%.*]] = select i1 [[X]], i32 41, i32 42, !prof [[PROF2:![0-9]+]]53; CHECK-NEXT: ret i32 [[ADD]]54;55 %ext = sext i1 %x to i3256 %add = add i32 %ext, 4257 ret i32 %add58}59 60define i5 @and_add(i1 %x, i1 %y) !prof !0 {61; CHECK-LABEL: define i5 @and_add(62; CHECK-SAME: i1 [[X:%.*]], i1 [[Y:%.*]]) !prof [[PROF0]] {63; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[X]], true64; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[Y]], [[TMP1]]65; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], i5 -2, i5 0, !prof [[PROF2]]66; CHECK-NEXT: ret i5 [[R]]67;68 %xz = zext i1 %x to i569 %ys = sext i1 %y to i570 %sub = add i5 %xz, %ys71 %r = and i5 %sub, 3072 ret i5 %r73}74 75define i32 @add_zext_zext_i1(i1 %a) !prof !0 {76; CHECK-LABEL: define i32 @add_zext_zext_i1(77; CHECK-SAME: i1 [[A:%.*]]) !prof [[PROF0]] {78; CHECK-NEXT: [[ADD:%.*]] = select i1 [[A]], i32 2, i32 0, !prof [[PROF2]]79; CHECK-NEXT: ret i32 [[ADD]]80;81 %zext = zext i1 %a to i3282 %add = add i32 %zext, %zext83 ret i32 %add84}85 86define i32 @no_count_no_branch_weights(i1 %a) {87; CHECK-LABEL: define i32 @no_count_no_branch_weights(88; CHECK-SAME: i1 [[A:%.*]]) {89; CHECK-NEXT: [[ADD:%.*]] = select i1 [[A]], i32 2, i32 090; CHECK-NEXT: ret i32 [[ADD]]91;92 %zext = zext i1 %a to i3293 %add = add i32 %zext, %zext94 ret i32 %add95}96 97 98!0 = !{!"function_entry_count", i64 1000}99!1 = !{!"branch_weights", i32 2, i32 3}100;.101; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1000}102; CHECK: [[PROF1]] = !{!"branch_weights", i32 2, i32 3}103; CHECK: [[PROF2]] = !{!"unknown", !"instcombine"}104;.105