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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X86 %}3; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefix=AARCH64 %}4 5 6define i1 @test(i32 %0, i32 %1, i32 %p) {7; X86-LABEL: define i1 @test(8; X86-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) {9; X86-NEXT: entry:10; X86-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 011; X86-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 012; X86-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer13; X86-NEXT: [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]14; X86-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer15; X86-NEXT: [[CMP6:%.*]] = icmp slt i32 0, [[P]]16; X86-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]17; X86-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])18; X86-NEXT: [[OP_RDX:%.*]] = select i1 [[TMP7]], i1 true, i1 [[CMP6]]19; X86-NEXT: [[OP_RDX1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP1]]20; X86-NEXT: [[TMP8:%.*]] = freeze i1 [[OP_RDX]]21; X86-NEXT: [[OP_RDX2:%.*]] = select i1 [[TMP8]], i1 true, i1 [[OP_RDX1]]22; X86-NEXT: ret i1 [[OP_RDX2]]23;24; AARCH64-LABEL: define i1 @test(25; AARCH64-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) {26; AARCH64-NEXT: entry:27; AARCH64-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 028; AARCH64-NEXT: [[SHL4:%.*]] = shl i32 0, [[TMP1]]29; AARCH64-NEXT: [[CMP5:%.*]] = icmp slt i32 [[SHL4]], 030; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP1]], i32 131; AARCH64-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>32; AARCH64-NEXT: [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]33; AARCH64-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[P]], i32 034; AARCH64-NEXT: [[TMP6:%.*]] = icmp slt <4 x i32> [[TMP4]], [[TMP5]]35; AARCH64-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP6]]36; AARCH64-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])37; AARCH64-NEXT: [[OP_RDX:%.*]] = select i1 [[TMP8]], i1 true, i1 [[CMP5]]38; AARCH64-NEXT: [[OP_RDX1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP1]]39; AARCH64-NEXT: [[TMP9:%.*]] = freeze i1 [[OP_RDX]]40; AARCH64-NEXT: [[OP_RDX2:%.*]] = select i1 [[TMP9]], i1 true, i1 [[OP_RDX1]]41; AARCH64-NEXT: ret i1 [[OP_RDX2]]42;43entry:44 %cmp1 = icmp sgt i32 %0, 045 %shl1 = shl i32 0, %146 %cmp2 = icmp slt i32 %shl1, 047 %2 = select i1 %cmp1, i1 true, i1 %cmp248 %shl2 = shl i32 0, %149 %cmp3 = icmp slt i32 %shl2, 050 %3 = select i1 %2, i1 true, i1 %cmp351 %shl3 = shl i32 0, %152 %cmp4 = icmp slt i32 %shl3, 053 %4 = select i1 %3, i1 true, i1 %cmp454 %shl4 = shl i32 0, %155 %cmp5 = icmp slt i32 %shl4, 056 %5 = select i1 %4, i1 true, i1 %cmp557 %cmp6 = icmp slt i32 0, %p58 %sel = select i1 %cmp1, i1 true, i1 %cmp659 %6 = or i1 %sel, %560 ret i1 %661}62